C166: ACCESS PROBLEM WITH XC16X ON-CHIP FLASH

Information in this article applies to:

• C166 Version 5

SYMPTOM

The Errata Sheets for XC161, XC164, and XC167 Infineon document a FCPUR X.162832 Flash Read Performance problem. This Flash problem is indicated by a Class B Trap with PACER=1 (bit 4 set in TFR). The problem depends on the operating temperature and the CPU frequency. To avoid this problem, Infineon recommends that you increase the wait states for Flash ROM (WSFLASH) in the IMBCTR control register as shown below:

For Ambient Temperatures -40 to 85 degrees Celsius the setting of WSFLASH should be:

• Fcpu <= 16MHz: 0 Wait states (WSFLASH=0).
• 16MHz < Fcpu <= 32MHz: 1 Wait state (WSFLASH=1).
• Fcpu > 32MHz: 2 Wait states (WSFLASH=2).

For Ambient Temperatures above 85 degrees Celsius the setting of WSFLASH should be:

• Fcpu <= 16MHz: 0 Wait states (WSFLASH=0).
• 16MHz < Fcpu <= 28MHz: 1 Wait state (WSFLASH=1).
• Fcpu > 28MHz: 2 Wait states (WSFLASH=2).

RESOLUTION

To set the wait states in your application, you must use startup code (START_V2.A66) version 5.05 or higher. This file may be downloaded (see the Attachments section below) or you may download the latest updates from the Keil Website. The waitstates for on-chip Flash ROM can be configured under CPU Configuration - Definitions for Internal Memory Block Control Register IBMCTR - WSFLASH: Wait States for the Flash Memory. Select the number of waitstates as required for your application.

MORE INFORMATION

• Refer to the Infineon Device Errata Sheets for more details.

SEE ALSO

• C166: IDENTIFY INSTRUCTION CAUSING CLASS B HARDWARE TRAP

ATTACHED FILES

Request the files attached to this knowledgebase article.

Last Reviewed: Saturday, May 28, 2005