CX51: WORKAROUND FOR P89C669 CORE.2 ERRATA
Information in this article applies to:
The Philips errata for the P89C669 describes a CORE.2 problem:
CORE2: Access to off-chip XDATA with MOVX @DPTR instruction
Introduction: MOVX @DPTR instruction is going to access off-chip located data byte if content of DPTR is greater than the address of the last available byte of on-chip XDATA memory space (AUXR.1=0).
Problem: If instruction MOVX @DPTR type is located at 1:upper7bits:lower16bits and an address of location pointed at via DPTR is off-chip, microcontroller will access byte at 0:upper7bits:(DPTR) instead of byte at 0:00:(DPTR).
Workaround: Instead of using MOVX @DPTR, EMOV @PR0(1) instruction with R3(R7)=0 can be used in systems designed with 23 bits wide external address interface. Code written in C language should use pointers to far data in this case rather than pointers to XDATA."
Does this errata imply that I cannot use the LARGE memory model with the P89C669? Is there a memory model that always uses EPTR/PRx accesses instead of MOVX?
There is no memory model that uses EPTR/PRx instructions instead of MOVX. However, the LARGE memory model can still be used when you limit access to the on-chip XRAM of the device. This can be done as follows:
Note: The on-chip XRAM size off the Philips P89C669 is just 300H Bytes and not 700H as it is configured in older releases of the Keil Device Database.
Last Reviewed: Sunday, October 29, 2006
of your data.