C51: Microchip/Atmel T89C51CC01 Internal EEPROM Support

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Information in this article applies to:

• C51 Version 6.23 and later

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QUESTION

I am using the example of writing to and reading from the 2K EEPROM space for the ATMEL WM T89C51RD2 and for the ATMEL WM T89C51CC01. Why does this program not read and write properly for the ATMEL WM T89C51CC01 internal 2K EEPROM?

ANSWER

The architecture for the internal EEPROM for the ATMEL WM T89C51CC01 is different than for the ATMEL WM T89C51RD2 or the Philips P89C51RD2. Therefore, the Keil example project for the ATMEL WM T89C51RD2 located at \Keil\C51\EXAMPLES\FarMemory\E2PROM for the 80C51RD2 will not work properly for the ATMEL WM T89C51CC01.

The 2k byte on-chip EEPROM memory block for the ATMEL WM T89C51CC01 is located at addresses 0000h to 07FFh of the XRAM memory space and is selected by setting control bits in the EECON register.

A read in the EEPROM memory is done with a MOVX instruction.

A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming). The number of data written on the page may vary from 1 to 128 bytes (the page size).

When programming, only the data written in the column latch is programmed and a ninth bit is used to obtain this feature. This provides the capability to program the whole memory by bytes, by page or by a number of bytes in a page. Indeed, each ninth bit is set when the writing the corresponding byte in a row and all these ninth bits are reset after the writing of the complete EEPROM row.

1) Write Data in the column latches:

Data is written by byte to the column latches as if to an external RAM memory. Out of the 11 address bits of the data pointer, the 4 MSBs are used for page selection (row) and 7 are used for byte selection. Between two EEPROM programming sessions, all the addresses in the column latches must stay on the same page, meaning that the 4 MSB must not be changed.

The following procedure writes to the column latches:

• Set bit EEE of EECON register
• Stretch the MOVX to accommodate the slow access time of the column latch (Set bit M0 of AUXR register)
• Load DPTR with the address to write
• Store in the Accumulator the data to be written
• Execute a MOVX @DPTR, A
• If needed, loop the three last instructions until the end of a 128 bytes page

2) Programming

The EEPROM programming includes the following actions:

• Writing one or more bytes of one page in the column latches. Normally, all bytes must belong to the same page; if not, the first page address will be latched and the others discarded.
• Launch the programming by writing the control sequence (54h followed by A4h) to the EECON register.
• EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that the EEPROM segment is not available for reading.
• The end of programming is indicated by a hardware clear of the EEBUSY flag.

3) Reading Data from the EEPROM

The following procedure reads the data stored in the EEPROM memory:

• Set bit EEE of EECON register
• Stretch the MOVX to accommodate the slow access time of the column latch (Set bit M0 of AUXR register)
• Load DPTR with the address to read
• Execute a MOVX A, @DPTR

MORE INFORMATION

• Refer to the ATMEL WM T89C51CC01 Data Sheet for more information on the EEPROM memory access.
• Refer to the Philips P89C51RD2 Data Sheet for more information on the EEPROM memory access.
• Refer to the ATMEL WM T89C51RD2 Data Sheet for more information on the EEPROM memory access.
• Refer to the \KEIL\C51\EXAMPLES\FarMemory\E2PROM directory for example EEPROM projects for T89C51RD2 and P89C51RD2

SEE ALSO

• C51: Accessing Internal EEPROM on Atmel 89LS8252
• C51: Offsets with Far Memory Access

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Last Reviewed: Thursday, February 25, 2021

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