C51: ACCESSING THE DS390 ON-CHIP 4K SRAM AND STACK
Information in this article applies to:
How do I configure the Keil C51 Tools for the Dallas 390 on-chip 4K SRAM and Stack?
You must configure the on-chip 4K SRAM and stack in both the startup code (START390.A51) and in µVision.
Configuring the 4K SRAM
In START390.A51, the internal data memory configuration bits (MCON.6 and MCON.7) are set by specifying the appropriate value for IDM as shown below.
; IDM1, IDM0: Internal Data Memory Configuration Bits (MCON.7, MCON.6) IDM EQU 0 ; 0 = 4KB on-chip SRAM location X:0x00F000 - X:0x00FFFF ; ; 1 = 4KB on-chip SRAM location X:0x000000 - X:0x000FFF ; ; 2 = 4KB on-chip SRAM location X:0x400000 - X:0x400FFF ; ; 3 = 4KB on-chip SRAM location X:0x400000 - X:0x400FFF ; and code memory C:0x400000 - C:0x400FFF
There are four options for the internal data memory:
Configuring the Stack
In START390.A51, the stack can be configured to use the 8051-compatible IDATA memory or the 1K on-chip XDATA memory.
; SA: Extend Stack Address Mode Enable (ACON.2) SA EQU 0 ; 0 = 8051 compatible stack in IDATA memory ; ; 1 = Use 1KB stack in on-chip XDATA space
If you use the on-chip SRAM for the stack, only 1K of space is used for the stack by default. You may increase this by changing the storage specification in the startup code.
RSEG ?STACK DS 1024
Note that you must use the PK51 Professional Developer's Kit Version 6.11 or later to obtain contiguous mode support for the Dallas 390.
More information about the Dallas 390 Contiguous mode support may be found in the README.TXT file found in the \KEIL\C51\EXAMPLES\DALLAS 390 directory of your installation.
The following Discussion Forum threads may provide information related to this topic.
Last Reviewed: Friday, April 16, 2004