C166: CPU.21 Errata Problems and FIXBFLD Directive

Information in this article applies to:

• C166 Version 3.12
• C166 Version 4.06

SYMPTOMS

If you use a C16x device affected by the CPU.21 BFLD instruction problem, you may need to upgrade to the latest Keil C166 compiler.

We have checked the C166 V3.xx and C166 V4.xx release for the CPU.21 problem described by Infineon and found the following:

C166 V3.xx generates BFLD instructions only in the following cases:

1. When you use the _bfld_ intrinsic function.
2. At the beginning of interrupt service routines when you use #pragma disable.
3. At the end of interrupt service routines when you use the FIX166 directive.

C166 V4.xx uses the BFLD instruction to optimize bit-field struct accesses. C166 V4.10 offers a new directive (FIXBFLD) that inserts an ATOMIC #1 instruction before every BFLD instruction that is not enclosed in an EXTR sequence. Detailed information may be found in \KEIL\C166\HLP\RELEASE.TXT of C166 Version 4.10.

The C166 Run-Time Library for C166 V3.xx and V4.xx uses BFLD instructions only in the START167.A66 file. This part of the code should be not affected by the CPU.21 problem.

The RTX166 Full Real-Time Operating system does not use BFLD instructions.

The RTX166 Tiny Version uses BFLD instructions to disable interrupts. We are currently evaluating if there can be potential problems in this code. If you use this operating system, you should modify the source code and add ATOMIC #1 instructions before the BFLD instructions. Then, rebuild the library.

SEE ALSO

• C166: FIXBFLD Directive
• C166: Version 4 Release Notes

Last Reviewed: Thursday, February 25, 2021