CMSIS-Core (Cortex-A)  Version 1.2.0
CMSIS-Core support for Cortex-A processor-based devices
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
core_ca.h File Reference

CMSIS Cortex-A Core Peripheral Access Layer Header File. More...

Data Structures

struct  CPSR_Type
 Bit field declaration for CPSR layout. More...
 
struct  SCTLR_Type
 Bit field declaration for SCTLR layout. More...
 
struct  ACTLR_Type
 Bit field declaration for ACTLR layout. More...
 
struct  CPACR_Type
 Bit field declaration for CPACR layout. More...
 
struct  DFSR_Type
 Bit field declaration for DFSR layout. More...
 
struct  IFSR_Type
 Bit field declaration for IFSR layout. More...
 
struct  ISR_Type
 Bit field declaration for ISR layout. More...
 
struct  L2C_310_TypeDef
 Union type to access the L2C_310 Cache Controller. More...
 
struct  GICDistributor_Type
 Structure type to access the Generic Interrupt Controller Distributor (GICD) More...
 
struct  GICInterface_Type
 Structure type to access the Generic Interrupt Controller Interface (GICC) More...
 
struct  Timer_Type
 Structure type to access the Private Timer. More...
 
union  CNTP_CTL_Type
 Physical Timer Control register. More...
 
struct  mmu_region_attributes_Type
 

Macros

#define __CORE_CA_H_GENERIC
 
#define __CA_CMSIS_VERSION_MAIN   (1U)
 [31:16] CMSIS-Core(A) main version More...
 
#define __CA_CMSIS_VERSION_SUB   (1U)
 [15:0] CMSIS-Core(A) sub version More...
 
#define __CA_CMSIS_VERSION
 CMSIS-Core(A) version number. More...
 
#define __FPU_USED   0U
 
#define __CORE_CA_H_DEPENDANT
 
#define __FPU_PRESENT   0U
 
#define __GIC_PRESENT   1U
 
#define __TIM_PRESENT   1U
 
#define __I   volatile
 Defines 'read only' permissions. More...
 
#define __O   volatile
 Defines 'write only' permissions. More...
 
#define __IO   volatile
 Defines 'read / write' permissions. More...
 
#define __IM   volatile const
 Defines 'read only' structure member permissions. More...
 
#define __OM   volatile
 Defines 'write only' structure member permissions. More...
 
#define __IOM   volatile
 Defines 'read / write' structure member permissions. More...
 
#define RESERVED(N, T)   T RESERVED##N;
 
#define CPSR_N_Pos   31U
 CPSR: N Position. More...
 
#define CPSR_N_Msk   (1UL << CPSR_N_Pos)
 CPSR: N Mask. More...
 
#define CPSR_Z_Pos   30U
 CPSR: Z Position. More...
 
#define CPSR_Z_Msk   (1UL << CPSR_Z_Pos)
 CPSR: Z Mask. More...
 
#define CPSR_C_Pos   29U
 CPSR: C Position. More...
 
#define CPSR_C_Msk   (1UL << CPSR_C_Pos)
 CPSR: C Mask. More...
 
#define CPSR_V_Pos   28U
 CPSR: V Position. More...
 
#define CPSR_V_Msk   (1UL << CPSR_V_Pos)
 CPSR: V Mask. More...
 
#define CPSR_Q_Pos   27U
 CPSR: Q Position. More...
 
#define CPSR_Q_Msk   (1UL << CPSR_Q_Pos)
 CPSR: Q Mask. More...
 
#define CPSR_IT0_Pos   25U
 CPSR: IT0 Position. More...
 
#define CPSR_IT0_Msk   (3UL << CPSR_IT0_Pos)
 CPSR: IT0 Mask. More...
 
#define CPSR_J_Pos   24U
 CPSR: J Position. More...
 
#define CPSR_J_Msk   (1UL << CPSR_J_Pos)
 CPSR: J Mask. More...
 
#define CPSR_GE_Pos   16U
 CPSR: GE Position. More...
 
#define CPSR_GE_Msk   (0xFUL << CPSR_GE_Pos)
 CPSR: GE Mask. More...
 
#define CPSR_IT1_Pos   10U
 CPSR: IT1 Position. More...
 
#define CPSR_IT1_Msk   (0x3FUL << CPSR_IT1_Pos)
 CPSR: IT1 Mask. More...
 
#define CPSR_E_Pos   9U
 CPSR: E Position. More...
 
#define CPSR_E_Msk   (1UL << CPSR_E_Pos)
 CPSR: E Mask. More...
 
#define CPSR_A_Pos   8U
 CPSR: A Position. More...
 
#define CPSR_A_Msk   (1UL << CPSR_A_Pos)
 CPSR: A Mask. More...
 
#define CPSR_I_Pos   7U
 CPSR: I Position. More...
 
#define CPSR_I_Msk   (1UL << CPSR_I_Pos)
 CPSR: I Mask. More...
 
#define CPSR_F_Pos   6U
 CPSR: F Position. More...
 
#define CPSR_F_Msk   (1UL << CPSR_F_Pos)
 CPSR: F Mask. More...
 
#define CPSR_T_Pos   5U
 CPSR: T Position. More...
 
#define CPSR_T_Msk   (1UL << CPSR_T_Pos)
 CPSR: T Mask. More...
 
#define CPSR_M_Pos   0U
 CPSR: M Position. More...
 
#define CPSR_M_Msk   (0x1FUL << CPSR_M_Pos)
 CPSR: M Mask. More...
 
#define CPSR_M_USR   0x10U
 CPSR: M User mode (PL0) More...
 
#define CPSR_M_FIQ   0x11U
 CPSR: M Fast Interrupt mode (PL1) More...
 
#define CPSR_M_IRQ   0x12U
 CPSR: M Interrupt mode (PL1) More...
 
#define CPSR_M_SVC   0x13U
 CPSR: M Supervisor mode (PL1) More...
 
#define CPSR_M_MON   0x16U
 CPSR: M Monitor mode (PL1) More...
 
#define CPSR_M_ABT   0x17U
 CPSR: M Abort mode (PL1) More...
 
#define CPSR_M_HYP   0x1AU
 CPSR: M Hypervisor mode (PL2) More...
 
#define CPSR_M_UND   0x1BU
 CPSR: M Undefined mode (PL1) More...
 
#define CPSR_M_SYS   0x1FU
 CPSR: M System mode (PL1) More...
 
#define SCTLR_TE_Pos   30U
 SCTLR: TE Position. More...
 
#define SCTLR_TE_Msk   (1UL << SCTLR_TE_Pos)
 SCTLR: TE Mask. More...
 
#define SCTLR_AFE_Pos   29U
 SCTLR: AFE Position. More...
 
#define SCTLR_AFE_Msk   (1UL << SCTLR_AFE_Pos)
 SCTLR: AFE Mask. More...
 
#define SCTLR_TRE_Pos   28U
 SCTLR: TRE Position. More...
 
#define SCTLR_TRE_Msk   (1UL << SCTLR_TRE_Pos)
 SCTLR: TRE Mask. More...
 
#define SCTLR_NMFI_Pos   27U
 SCTLR: NMFI Position. More...
 
#define SCTLR_NMFI_Msk   (1UL << SCTLR_NMFI_Pos)
 SCTLR: NMFI Mask. More...
 
#define SCTLR_EE_Pos   25U
 SCTLR: EE Position. More...
 
#define SCTLR_EE_Msk   (1UL << SCTLR_EE_Pos)
 SCTLR: EE Mask. More...
 
#define SCTLR_VE_Pos   24U
 SCTLR: VE Position. More...
 
#define SCTLR_VE_Msk   (1UL << SCTLR_VE_Pos)
 SCTLR: VE Mask. More...
 
#define SCTLR_U_Pos   22U
 SCTLR: U Position. More...
 
#define SCTLR_U_Msk   (1UL << SCTLR_U_Pos)
 SCTLR: U Mask. More...
 
#define SCTLR_FI_Pos   21U
 SCTLR: FI Position. More...
 
#define SCTLR_FI_Msk   (1UL << SCTLR_FI_Pos)
 SCTLR: FI Mask. More...
 
#define SCTLR_UWXN_Pos   20U
 SCTLR: UWXN Position. More...
 
#define SCTLR_UWXN_Msk   (1UL << SCTLR_UWXN_Pos)
 SCTLR: UWXN Mask. More...
 
#define SCTLR_WXN_Pos   19U
 SCTLR: WXN Position. More...
 
#define SCTLR_WXN_Msk   (1UL << SCTLR_WXN_Pos)
 SCTLR: WXN Mask. More...
 
#define SCTLR_HA_Pos   17U
 SCTLR: HA Position. More...
 
#define SCTLR_HA_Msk   (1UL << SCTLR_HA_Pos)
 SCTLR: HA Mask. More...
 
#define SCTLR_RR_Pos   14U
 SCTLR: RR Position. More...
 
#define SCTLR_RR_Msk   (1UL << SCTLR_RR_Pos)
 SCTLR: RR Mask. More...
 
#define SCTLR_V_Pos   13U
 SCTLR: V Position. More...
 
#define SCTLR_V_Msk   (1UL << SCTLR_V_Pos)
 SCTLR: V Mask. More...
 
#define SCTLR_I_Pos   12U
 SCTLR: I Position. More...
 
#define SCTLR_I_Msk   (1UL << SCTLR_I_Pos)
 SCTLR: I Mask. More...
 
#define SCTLR_Z_Pos   11U
 SCTLR: Z Position. More...
 
#define SCTLR_Z_Msk   (1UL << SCTLR_Z_Pos)
 SCTLR: Z Mask. More...
 
#define SCTLR_SW_Pos   10U
 SCTLR: SW Position. More...
 
#define SCTLR_SW_Msk   (1UL << SCTLR_SW_Pos)
 SCTLR: SW Mask. More...
 
#define SCTLR_B_Pos   7U
 SCTLR: B Position. More...
 
#define SCTLR_B_Msk   (1UL << SCTLR_B_Pos)
 SCTLR: B Mask. More...
 
#define SCTLR_CP15BEN_Pos   5U
 SCTLR: CP15BEN Position. More...
 
#define SCTLR_CP15BEN_Msk   (1UL << SCTLR_CP15BEN_Pos)
 SCTLR: CP15BEN Mask. More...
 
#define SCTLR_C_Pos   2U
 SCTLR: C Position. More...
 
#define SCTLR_C_Msk   (1UL << SCTLR_C_Pos)
 SCTLR: C Mask. More...
 
#define SCTLR_A_Pos   1U
 SCTLR: A Position. More...
 
#define SCTLR_A_Msk   (1UL << SCTLR_A_Pos)
 SCTLR: A Mask. More...
 
#define SCTLR_M_Pos   0U
 SCTLR: M Position. More...
 
#define SCTLR_M_Msk   (1UL << SCTLR_M_Pos)
 SCTLR: M Mask. More...
 
#define ACTLR_DDI_Pos   28U
 ACTLR: DDI Position. More...
 
#define ACTLR_DDI_Msk   (1UL << ACTLR_DDI_Pos)
 ACTLR: DDI Mask. More...
 
#define ACTLR_DBDI_Pos   28U
 ACTLR: DBDI Position. More...
 
#define ACTLR_DBDI_Msk   (1UL << ACTLR_DBDI_Pos)
 ACTLR: DBDI Mask. More...
 
#define ACTLR_BTDIS_Pos   18U
 ACTLR: BTDIS Position. More...
 
#define ACTLR_BTDIS_Msk   (1UL << ACTLR_BTDIS_Pos)
 ACTLR: BTDIS Mask. More...
 
#define ACTLR_RSDIS_Pos   17U
 ACTLR: RSDIS Position. More...
 
#define ACTLR_RSDIS_Msk   (1UL << ACTLR_RSDIS_Pos)
 ACTLR: RSDIS Mask. More...
 
#define ACTLR_BP_Pos   15U
 ACTLR: BP Position. More...
 
#define ACTLR_BP_Msk   (3UL << ACTLR_BP_Pos)
 ACTLR: BP Mask. More...
 
#define ACTLR_DDVM_Pos   15U
 ACTLR: DDVM Position. More...
 
#define ACTLR_DDVM_Msk   (1UL << ACTLR_DDVM_Pos)
 ACTLR: DDVM Mask. More...
 
#define ACTLR_L1PCTL_Pos   13U
 ACTLR: L1PCTL Position. More...
 
#define ACTLR_L1PCTL_Msk   (3UL << ACTLR_L1PCTL_Pos)
 ACTLR: L1PCTL Mask. More...
 
#define ACTLR_RADIS_Pos   12U
 ACTLR: RADIS Position. More...
 
#define ACTLR_RADIS_Msk   (1UL << ACTLR_RADIS_Pos)
 ACTLR: RADIS Mask. More...
 
#define ACTLR_L1RADIS_Pos   12U
 ACTLR: L1RADIS Position. More...
 
#define ACTLR_L1RADIS_Msk   (1UL << ACTLR_L1RADIS_Pos)
 ACTLR: L1RADIS Mask. More...
 
#define ACTLR_DWBST_Pos   11U
 ACTLR: DWBST Position. More...
 
#define ACTLR_DWBST_Msk   (1UL << ACTLR_DWBST_Pos)
 ACTLR: DWBST Mask. More...
 
#define ACTLR_L2RADIS_Pos   11U
 ACTLR: L2RADIS Position. More...
 
#define ACTLR_L2RADIS_Msk   (1UL << ACTLR_L2RADIS_Pos)
 ACTLR: L2RADIS Mask. More...
 
#define ACTLR_DODMBS_Pos   10U
 ACTLR: DODMBS Position. More...
 
#define ACTLR_DODMBS_Msk   (1UL << ACTLR_DODMBS_Pos)
 ACTLR: DODMBS Mask. More...
 
#define ACTLR_PARITY_Pos   9U
 ACTLR: PARITY Position. More...
 
#define ACTLR_PARITY_Msk   (1UL << ACTLR_PARITY_Pos)
 ACTLR: PARITY Mask. More...
 
#define ACTLR_AOW_Pos   8U
 ACTLR: AOW Position. More...
 
#define ACTLR_AOW_Msk   (1UL << ACTLR_AOW_Pos)
 ACTLR: AOW Mask. More...
 
#define ACTLR_EXCL_Pos   7U
 ACTLR: EXCL Position. More...
 
#define ACTLR_EXCL_Msk   (1UL << ACTLR_EXCL_Pos)
 ACTLR: EXCL Mask. More...
 
#define ACTLR_SMP_Pos   6U
 ACTLR: SMP Position. More...
 
#define ACTLR_SMP_Msk   (1UL << ACTLR_SMP_Pos)
 ACTLR: SMP Mask. More...
 
#define ACTLR_WFLZM_Pos   3U
 ACTLR: WFLZM Position. More...
 
#define ACTLR_WFLZM_Msk   (1UL << ACTLR_WFLZM_Pos)
 ACTLR: WFLZM Mask. More...
 
#define ACTLR_L1PE_Pos   2U
 ACTLR: L1PE Position. More...
 
#define ACTLR_L1PE_Msk   (1UL << ACTLR_L1PE_Pos)
 ACTLR: L1PE Mask. More...
 
#define ACTLR_FW_Pos   0U
 ACTLR: FW Position. More...
 
#define ACTLR_FW_Msk   (1UL << ACTLR_FW_Pos)
 ACTLR: FW Mask. More...
 
#define CPACR_ASEDIS_Pos   31U
 CPACR: ASEDIS Position. More...
 
#define CPACR_ASEDIS_Msk   (1UL << CPACR_ASEDIS_Pos)
 CPACR: ASEDIS Mask. More...
 
#define CPACR_D32DIS_Pos   30U
 CPACR: D32DIS Position. More...
 
#define CPACR_D32DIS_Msk   (1UL << CPACR_D32DIS_Pos)
 CPACR: D32DIS Mask. More...
 
#define CPACR_TRCDIS_Pos   28U
 CPACR: D32DIS Position. More...
 
#define CPACR_TRCDIS_Msk   (1UL << CPACR_D32DIS_Pos)
 CPACR: D32DIS Mask. More...
 
#define CPACR_CP_Pos_(n)   (n*2U)
 CPACR: CPn Position. More...
 
#define CPACR_CP_Msk_(n)   (3UL << CPACR_CP_Pos_(n))
 CPACR: CPn Mask. More...
 
#define CPACR_CP_NA   0U
 CPACR CPn field: Access denied. More...
 
#define CPACR_CP_PL1   1U
 CPACR CPn field: Accessible from PL1 only. More...
 
#define CPACR_CP_FA   3U
 CPACR CPn field: Full access. More...
 
#define DFSR_CM_Pos   13U
 DFSR: CM Position. More...
 
#define DFSR_CM_Msk   (1UL << DFSR_CM_Pos)
 DFSR: CM Mask. More...
 
#define DFSR_Ext_Pos   12U
 DFSR: Ext Position. More...
 
#define DFSR_Ext_Msk   (1UL << DFSR_Ext_Pos)
 DFSR: Ext Mask. More...
 
#define DFSR_WnR_Pos   11U
 DFSR: WnR Position. More...
 
#define DFSR_WnR_Msk   (1UL << DFSR_WnR_Pos)
 DFSR: WnR Mask. More...
 
#define DFSR_FS1_Pos   10U
 DFSR: FS1 Position. More...
 
#define DFSR_FS1_Msk   (1UL << DFSR_FS1_Pos)
 DFSR: FS1 Mask. More...
 
#define DFSR_LPAE_Pos   9U
 DFSR: LPAE Position. More...
 
#define DFSR_LPAE_Msk   (1UL << DFSR_LPAE_Pos)
 DFSR: LPAE Mask. More...
 
#define DFSR_Domain_Pos   4U
 DFSR: Domain Position. More...
 
#define DFSR_Domain_Msk   (0xFUL << DFSR_Domain_Pos)
 DFSR: Domain Mask. More...
 
#define DFSR_FS0_Pos   0U
 DFSR: FS0 Position. More...
 
#define DFSR_FS0_Msk   (0xFUL << DFSR_FS0_Pos)
 DFSR: FS0 Mask. More...
 
#define DFSR_STATUS_Pos   0U
 DFSR: STATUS Position. More...
 
#define DFSR_STATUS_Msk   (0x3FUL << DFSR_STATUS_Pos)
 DFSR: STATUS Mask. More...
 
#define IFSR_ExT_Pos   12U
 IFSR: ExT Position. More...
 
#define IFSR_ExT_Msk   (1UL << IFSR_ExT_Pos)
 IFSR: ExT Mask. More...
 
#define IFSR_FS1_Pos   10U
 IFSR: FS1 Position. More...
 
#define IFSR_FS1_Msk   (1UL << IFSR_FS1_Pos)
 IFSR: FS1 Mask. More...
 
#define IFSR_LPAE_Pos   9U
 IFSR: LPAE Position. More...
 
#define IFSR_LPAE_Msk   (0x1UL << IFSR_LPAE_Pos)
 IFSR: LPAE Mask. More...
 
#define IFSR_FS0_Pos   0U
 IFSR: FS0 Position. More...
 
#define IFSR_FS0_Msk   (0xFUL << IFSR_FS0_Pos)
 IFSR: FS0 Mask. More...
 
#define IFSR_STATUS_Pos   0U
 IFSR: STATUS Position. More...
 
#define IFSR_STATUS_Msk   (0x3FUL << IFSR_STATUS_Pos)
 IFSR: STATUS Mask. More...
 
#define ISR_A_Pos   13U
 ISR: A Position. More...
 
#define ISR_A_Msk   (1UL << ISR_A_Pos)
 ISR: A Mask. More...
 
#define ISR_I_Pos   12U
 ISR: I Position. More...
 
#define ISR_I_Msk   (1UL << ISR_I_Pos)
 ISR: I Mask. More...
 
#define ISR_F_Pos   11U
 ISR: F Position. More...
 
#define ISR_F_Msk   (1UL << ISR_F_Pos)
 ISR: F Mask. More...
 
#define DACR_D_Pos_(n)   (2U*n)
 DACR: Dn Position. More...
 
#define DACR_D_Msk_(n)   (3UL << DACR_D_Pos_(n))
 DACR: Dn Mask. More...
 
#define DACR_Dn_NOACCESS   0U
 DACR Dn field: No access. More...
 
#define DACR_Dn_CLIENT   1U
 DACR Dn field: Client. More...
 
#define DACR_Dn_MANAGER   3U
 DACR Dn field: Manager. More...
 
#define _VAL2FLD(field, value)   (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
 Mask and shift a bit field value for use in a register bit range. More...
 
#define _FLD2VAL(field, value)   (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
 Mask and shift a register value to extract a bit filed value. More...
 
#define L2C_310   ((L2C_310_TypeDef *)L2C_310_BASE)
 L2C_310 register set access pointer. More...
 
#define GICDistributor   ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE )
 GIC Distributor register set access pointer. More...
 
#define GICInterface   ((GICInterface_Type *) GIC_INTERFACE_BASE )
 GIC Interface register set access pointer. More...
 
#define PTIM   ((Timer_Type *) TIMER_BASE )
 Timer register struct. More...
 
#define GIC_SetSecurity   GIC_SetGroup
 
#define GIC_GetSecurity   GIC_GetGroup
 
#define SECTION_DESCRIPTOR   (0x2)
 
#define SECTION_MASK   (0xFFFFFFFC)
 
#define SECTION_TEXCB_MASK   (0xFFFF8FF3)
 
#define SECTION_B_SHIFT   (2)
 
#define SECTION_C_SHIFT   (3)
 
#define SECTION_TEX0_SHIFT   (12)
 
#define SECTION_TEX1_SHIFT   (13)
 
#define SECTION_TEX2_SHIFT   (14)
 
#define SECTION_XN_MASK   (0xFFFFFFEF)
 
#define SECTION_XN_SHIFT   (4)
 
#define SECTION_DOMAIN_MASK   (0xFFFFFE1F)
 
#define SECTION_DOMAIN_SHIFT   (5)
 
#define SECTION_P_MASK   (0xFFFFFDFF)
 
#define SECTION_P_SHIFT   (9)
 
#define SECTION_AP_MASK   (0xFFFF73FF)
 
#define SECTION_AP_SHIFT   (10)
 
#define SECTION_AP2_SHIFT   (15)
 
#define SECTION_S_MASK   (0xFFFEFFFF)
 
#define SECTION_S_SHIFT   (16)
 
#define SECTION_NG_MASK   (0xFFFDFFFF)
 
#define SECTION_NG_SHIFT   (17)
 
#define SECTION_NS_MASK   (0xFFF7FFFF)
 
#define SECTION_NS_SHIFT   (19)
 
#define PAGE_L1_DESCRIPTOR   (0x1)
 
#define PAGE_L1_MASK   (0xFFFFFFFC)
 
#define PAGE_L2_4K_DESC   (0x2)
 
#define PAGE_L2_4K_MASK   (0xFFFFFFFD)
 
#define PAGE_L2_64K_DESC   (0x1)
 
#define PAGE_L2_64K_MASK   (0xFFFFFFFC)
 
#define PAGE_4K_TEXCB_MASK   (0xFFFFFE33)
 
#define PAGE_4K_B_SHIFT   (2)
 
#define PAGE_4K_C_SHIFT   (3)
 
#define PAGE_4K_TEX0_SHIFT   (6)
 
#define PAGE_4K_TEX1_SHIFT   (7)
 
#define PAGE_4K_TEX2_SHIFT   (8)
 
#define PAGE_64K_TEXCB_MASK   (0xFFFF8FF3)
 
#define PAGE_64K_B_SHIFT   (2)
 
#define PAGE_64K_C_SHIFT   (3)
 
#define PAGE_64K_TEX0_SHIFT   (12)
 
#define PAGE_64K_TEX1_SHIFT   (13)
 
#define PAGE_64K_TEX2_SHIFT   (14)
 
#define PAGE_TEXCB_MASK   (0xFFFF8FF3)
 
#define PAGE_B_SHIFT   (2)
 
#define PAGE_C_SHIFT   (3)
 
#define PAGE_TEX_SHIFT   (12)
 
#define PAGE_XN_4K_MASK   (0xFFFFFFFE)
 
#define PAGE_XN_4K_SHIFT   (0)
 
#define PAGE_XN_64K_MASK   (0xFFFF7FFF)
 
#define PAGE_XN_64K_SHIFT   (15)
 
#define PAGE_DOMAIN_MASK   (0xFFFFFE1F)
 
#define PAGE_DOMAIN_SHIFT   (5)
 
#define PAGE_P_MASK   (0xFFFFFDFF)
 
#define PAGE_P_SHIFT   (9)
 
#define PAGE_AP_MASK   (0xFFFFFDCF)
 
#define PAGE_AP_SHIFT   (4)
 
#define PAGE_AP2_SHIFT   (9)
 
#define PAGE_S_MASK   (0xFFFFFBFF)
 
#define PAGE_S_SHIFT   (10)
 
#define PAGE_NG_MASK   (0xFFFFF7FF)
 
#define PAGE_NG_SHIFT   (11)
 
#define PAGE_NS_MASK   (0xFFFFFFF7)
 
#define PAGE_NS_SHIFT   (3)
 
#define OFFSET_1M   (0x00100000)
 
#define OFFSET_64K   (0x00010000)
 
#define OFFSET_4K   (0x00001000)
 
#define DESCRIPTOR_FAULT   (0x00000000)
 
#define section_normal(descriptor_l1, region)
 
#define section_normal_nc(descriptor_l1, region)
 
#define section_normal_cod(descriptor_l1, region)
 
#define section_normal_ro(descriptor_l1, region)
 
#define section_normal_rw(descriptor_l1, region)
 
#define section_so(descriptor_l1, region)
 
#define section_device_ro(descriptor_l1, region)
 
#define section_device_rw(descriptor_l1, region)
 
#define page4k_device_rw(descriptor_l1, descriptor_l2, region)
 
#define page64k_device_rw(descriptor_l1, descriptor_l2, region)
 

Enumerations

enum  mmu_region_size_Type {
  SECTION,
  PAGE_4k,
  PAGE_64k
}
 
enum  mmu_memory_Type {
  NORMAL,
  DEVICE,
  SHARED_DEVICE,
  NON_SHARED_DEVICE,
  STRONGLY_ORDERED
}
 
enum  mmu_cacheability_Type {
  NON_CACHEABLE,
  WB_WA,
  WT,
  WB_NO_WA
}
 
enum  mmu_ecc_check_Type {
  ECC_DISABLED,
  ECC_ENABLED
}
 
enum  mmu_execute_Type {
  EXECUTE,
  NON_EXECUTE
}
 
enum  mmu_global_Type {
  GLOBAL,
  NON_GLOBAL
}
 
enum  mmu_shared_Type {
  NON_SHARED,
  SHARED
}
 
enum  mmu_secure_Type {
  SECURE,
  NON_SECURE
}
 
enum  mmu_access_Type {
  NO_ACCESS,
  RW,
  READ
}
 

Functions

__STATIC_FORCEINLINE void L1C_EnableCaches (void)
 Enable Caches by setting I and C bits in SCTLR register. More...
 
__STATIC_FORCEINLINE void L1C_DisableCaches (void)
 Disable Caches by clearing I and C bits in SCTLR register. More...
 
__STATIC_FORCEINLINE void L1C_EnableBTAC (void)
 Enable Branch Prediction by setting Z bit in SCTLR register. More...
 
__STATIC_FORCEINLINE void L1C_DisableBTAC (void)
 Disable Branch Prediction by clearing Z bit in SCTLR register. More...
 
__STATIC_FORCEINLINE void L1C_InvalidateBTAC (void)
 Invalidate entire branch predictor array. More...
 
__STATIC_FORCEINLINE void L1C_InvalidateICacheAll (void)
 Invalidate the whole instruction cache. More...
 
__STATIC_FORCEINLINE void L1C_CleanDCacheMVA (void *va)
 Clean data cache line by address. More...
 
__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA (void *va)
 Invalidate data cache line by address. More...
 
__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA (void *va)
 Clean and Invalidate data cache by address. More...
 
__STATIC_FORCEINLINE uint8_t __log2_up (uint32_t n)
 Calculate log2 rounded up. More...
 
__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay (uint32_t level, uint32_t maint)
 Apply cache maintenance to given cache level. More...
 
__STATIC_FORCEINLINE void L1C_CleanInvalidateCache (uint32_t op)
 Clean and Invalidate the entire data or unified cache Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. More...
 
CMSIS_DEPRECATED
__STATIC_FORCEINLINE void 
__L1C_CleanInvalidateCache (uint32_t op)
 Clean and Invalidate the entire data or unified cache Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. More...
 
__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll (void)
 Invalidate the whole data cache. More...
 
__STATIC_FORCEINLINE void L1C_CleanDCacheAll (void)
 Clean the whole data cache. More...
 
__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll (void)
 Clean and invalidate the whole data cache. More...
 
__STATIC_INLINE void L2C_Sync (void)
 Cache Sync operation by writing CACHE_SYNC register. More...
 
__STATIC_INLINE int L2C_GetID (void)
 Read cache controller cache ID from CACHE_ID register. More...
 
__STATIC_INLINE int L2C_GetType (void)
 Read cache controller cache type from CACHE_TYPE register. More...
 
__STATIC_INLINE void L2C_InvAllByWay (void)
 Invalidate all cache by way. More...
 
__STATIC_INLINE void L2C_CleanInvAllByWay (void)
 Clean and Invalidate all cache by way. More...
 
__STATIC_INLINE void L2C_Enable (void)
 Enable Level 2 Cache. More...
 
__STATIC_INLINE void L2C_Disable (void)
 Disable Level 2 Cache. More...
 
__STATIC_INLINE void L2C_InvPa (void *pa)
 Invalidate cache by physical address. More...
 
__STATIC_INLINE void L2C_CleanPa (void *pa)
 Clean cache by physical address. More...
 
__STATIC_INLINE void L2C_CleanInvPa (void *pa)
 Clean and invalidate cache by physical address. More...
 
__STATIC_INLINE void GIC_EnableDistributor (void)
 Enable the interrupt distributor using the GIC's CTLR register. More...
 
__STATIC_INLINE void GIC_DisableDistributor (void)
 Disable the interrupt distributor using the GIC's CTLR register. More...
 
__STATIC_INLINE uint32_t GIC_DistributorInfo (void)
 Read the GIC's TYPER register. More...
 
__STATIC_INLINE uint32_t GIC_DistributorImplementer (void)
 Reads the GIC's IIDR register. More...
 
__STATIC_INLINE void GIC_SetTarget (IRQn_Type IRQn, uint32_t cpu_target)
 Sets the GIC's ITARGETSR register for the given interrupt. More...
 
__STATIC_INLINE uint32_t GIC_GetTarget (IRQn_Type IRQn)
 Read the GIC's ITARGETSR register. More...
 
__STATIC_INLINE void GIC_EnableInterface (void)
 Enable the CPU's interrupt interface. More...
 
__STATIC_INLINE void GIC_DisableInterface (void)
 Disable the CPU's interrupt interface. More...
 
__STATIC_INLINE IRQn_Type GIC_AcknowledgePending (void)
 Read the CPU's IAR register. More...
 
__STATIC_INLINE void GIC_EndInterrupt (IRQn_Type IRQn)
 Writes the given interrupt number to the CPU's EOIR register. More...
 
__STATIC_INLINE void GIC_EnableIRQ (IRQn_Type IRQn)
 Enables the given interrupt using GIC's ISENABLER register. More...
 
__STATIC_INLINE uint32_t GIC_GetEnableIRQ (IRQn_Type IRQn)
 Get interrupt enable status using GIC's ISENABLER register. More...
 
__STATIC_INLINE void GIC_DisableIRQ (IRQn_Type IRQn)
 Disables the given interrupt using GIC's ICENABLER register. More...
 
__STATIC_INLINE uint32_t GIC_GetPendingIRQ (IRQn_Type IRQn)
 Get interrupt pending status from GIC's ISPENDR register. More...
 
__STATIC_INLINE void GIC_SetPendingIRQ (IRQn_Type IRQn)
 Sets the given interrupt as pending using GIC's ISPENDR register. More...
 
__STATIC_INLINE void GIC_ClearPendingIRQ (IRQn_Type IRQn)
 Clears the given interrupt from being pending using GIC's ICPENDR register. More...
 
__STATIC_INLINE void GIC_SetConfiguration (IRQn_Type IRQn, uint32_t int_config)
 Sets the interrupt configuration using GIC's ICFGR register. More...
 
__STATIC_INLINE uint32_t GIC_GetConfiguration (IRQn_Type IRQn)
 Get the interrupt configuration from the GIC's ICFGR register. More...
 
__STATIC_INLINE void GIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
 Set the priority for the given interrupt in the GIC's IPRIORITYR register. More...
 
__STATIC_INLINE uint32_t GIC_GetPriority (IRQn_Type IRQn)
 Read the current interrupt priority from GIC's IPRIORITYR register. More...
 
__STATIC_INLINE void GIC_SetInterfacePriorityMask (uint32_t priority)
 Set the interrupt priority mask using CPU's PMR register. More...
 
__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask (void)
 Read the current interrupt priority mask from CPU's PMR register. More...
 
__STATIC_INLINE void GIC_SetBinaryPoint (uint32_t binary_point)
 Configures the group priority and subpriority split point using CPU's BPR register. More...
 
__STATIC_INLINE uint32_t GIC_GetBinaryPoint (void)
 Read the current group priority and subpriority split point from CPU's BPR register. More...
 
__STATIC_INLINE uint32_t GIC_GetIRQStatus (IRQn_Type IRQn)
 Get the status for a given interrupt. More...
 
__STATIC_INLINE void GIC_SendSGI (IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
 Generate a software interrupt using GIC's SGIR register. More...
 
__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ (void)
 Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. More...
 
__STATIC_INLINE uint32_t GIC_GetInterfaceId (void)
 Provides information about the implementer and revision of the CPU interface. More...
 
__STATIC_INLINE void GIC_SetGroup (IRQn_Type IRQn, uint32_t group)
 Set the interrupt group from the GIC's IGROUPR register. More...
 
__STATIC_INLINE uint32_t GIC_GetGroup (IRQn_Type IRQn)
 Get the interrupt group from the GIC's IGROUPR register. More...
 
__STATIC_INLINE void GIC_DistInit (void)
 Initialize the interrupt distributor. More...
 
__STATIC_INLINE void GIC_CPUInterfaceInit (void)
 Initialize the CPU's interrupt interface. More...
 
__STATIC_INLINE void GIC_Enable (void)
 Initialize and enable the GIC. More...
 
__STATIC_INLINE void PL1_SetCounterFrequency (uint32_t value)
 Configures the frequency the timer shall run at. More...
 
__STATIC_INLINE void PL1_SetLoadValue (uint32_t value)
 Sets the reset value of the timer. More...
 
__STATIC_INLINE uint32_t PL1_GetCurrentValue (void)
 Get the current counter value. More...
 
__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue (void)
 Get the current physical counter value. More...
 
__STATIC_INLINE void PL1_SetPhysicalCompareValue (uint64_t value)
 Set the physical compare value. More...
 
__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue (void)
 Get the physical compare value. More...
 
__STATIC_INLINE void PL1_SetControl (uint32_t value)
 Configure the timer by setting the control value. More...
 
__STATIC_INLINE uint32_t PL1_GetControl (void)
 Get the control value. More...
 
__STATIC_INLINE void PTIM_SetLoadValue (uint32_t value)
 Set the load value to timers LOAD register. More...
 
__STATIC_INLINE uint32_t PTIM_GetLoadValue (void)
 Get the load value from timers LOAD register. More...
 
__STATIC_INLINE void PTIM_SetCurrentValue (uint32_t value)
 Set current counter value from its COUNTER register. More...
 
__STATIC_INLINE uint32_t PTIM_GetCurrentValue (void)
 Get current counter value from timers COUNTER register. More...
 
__STATIC_INLINE void PTIM_SetControl (uint32_t value)
 Configure the timer using its CONTROL register. More...
 
__STATIC_INLINE uint32_t PTIM_GetControl (void)
 
__STATIC_INLINE uint32_t PTIM_GetEventFlag (void)
 
__STATIC_INLINE void PTIM_ClearEventFlag (void)
 
__STATIC_INLINE int MMU_XNSection (uint32_t *descriptor_l1, mmu_execute_Type xn)
 Set section execution-never attribute. More...
 
__STATIC_INLINE int MMU_DomainSection (uint32_t *descriptor_l1, uint8_t domain)
 Set section domain. More...
 
__STATIC_INLINE int MMU_PSection (uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
 Set section parity check. More...
 
__STATIC_INLINE int MMU_APSection (uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
 Set section access privileges. More...
 
__STATIC_INLINE int MMU_SharedSection (uint32_t *descriptor_l1, mmu_shared_Type s_bit)
 Set section shareability. More...
 
__STATIC_INLINE int MMU_GlobalSection (uint32_t *descriptor_l1, mmu_global_Type g_bit)
 Set section Global attribute. More...
 
__STATIC_INLINE int MMU_SecureSection (uint32_t *descriptor_l1, mmu_secure_Type s_bit)
 Set section Security attribute. More...
 
__STATIC_INLINE int MMU_XNPage (uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
 Set 4k/64k page execution-never attribute. More...
 
__STATIC_INLINE int MMU_DomainPage (uint32_t *descriptor_l1, uint8_t domain)
 Set 4k/64k page domain. More...
 
__STATIC_INLINE int MMU_PPage (uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
 Set 4k/64k page parity check. More...
 
__STATIC_INLINE int MMU_APPage (uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
 Set 4k/64k page access privileges. More...
 
__STATIC_INLINE int MMU_SharedPage (uint32_t *descriptor_l2, mmu_shared_Type s_bit)
 Set 4k/64k page shareability. More...
 
__STATIC_INLINE int MMU_GlobalPage (uint32_t *descriptor_l2, mmu_global_Type g_bit)
 Set 4k/64k page Global attribute. More...
 
__STATIC_INLINE int MMU_SecurePage (uint32_t *descriptor_l1, mmu_secure_Type s_bit)
 Set 4k/64k page Security attribute. More...
 
__STATIC_INLINE int MMU_MemorySection (uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
 Set Section memory attributes. More...
 
__STATIC_INLINE int MMU_MemoryPage (uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
 Set 4k/64k page memory attributes. More...
 
__STATIC_INLINE int MMU_GetSectionDescriptor (uint32_t *descriptor, mmu_region_attributes_Type reg)
 Create a L1 section descriptor. More...
 
__STATIC_INLINE int MMU_GetPageDescriptor (uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
 Create a L1 and L2 4k/64k page descriptor. More...
 
__STATIC_INLINE void MMU_TTSection (uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
 Create a 1MB Section. More...
 
__STATIC_INLINE void MMU_TTPage4k (uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2)
 Create a 4k page entry. More...
 
__STATIC_INLINE void MMU_TTPage64k (uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2)
 Create a 64k page entry. More...
 
__STATIC_INLINE void MMU_Enable (void)
 Enable MMU. More...
 
__STATIC_INLINE void MMU_Disable (void)
 Disable MMU. More...
 
__STATIC_INLINE void MMU_InvalidateTLB (void)
 Invalidate entire unified TLB. More...
 

Description

Version
V1.0.3
Date
28. January 2020

Macro Definition Documentation

#define __CORE_CA_H_DEPENDANT
#define __CORE_CA_H_GENERIC
#define __FPU_PRESENT   0U
#define __FPU_USED   0U
#define __GIC_PRESENT   1U
#define __I   volatile
#define __IM   volatile const
#define __IO   volatile
#define __IOM   volatile
#define __O   volatile
#define __OM   volatile
#define __TIM_PRESENT   1U
#define _FLD2VAL (   field,
  value 
)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
Parameters
[in]fieldName of the register bit field.
[in]valueValue of register. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted bit field value.
#define _VAL2FLD (   field,
  value 
)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
Parameters
[in]fieldName of the register bit field.
[in]valueValue of the bit field. This parameter is interpreted as an uint32_t type.
Returns
Masked and shifted value.
#define GIC_GetSecurity   GIC_GetGroup
#define GIC_SetSecurity   GIC_SetGroup
#define PAGE_4K_TEXCB_MASK   (0xFFFFFE33)
#define PAGE_64K_TEXCB_MASK   (0xFFFF8FF3)
#define PAGE_AP_MASK   (0xFFFFFDCF)
#define PAGE_DOMAIN_MASK   (0xFFFFFE1F)
#define PAGE_L1_MASK   (0xFFFFFFFC)
#define PAGE_L2_4K_MASK   (0xFFFFFFFD)
#define PAGE_L2_64K_MASK   (0xFFFFFFFC)
#define PAGE_NG_MASK   (0xFFFFF7FF)
#define PAGE_NS_MASK   (0xFFFFFFF7)
#define PAGE_P_MASK   (0xFFFFFDFF)
#define PAGE_S_MASK   (0xFFFFFBFF)
#define PAGE_TEXCB_MASK   (0xFFFF8FF3)
#define PAGE_XN_4K_MASK   (0xFFFFFFFE)
#define PAGE_XN_64K_MASK   (0xFFFF7FFF)
#define RESERVED (   N,
 
)    T RESERVED##N;
#define SECTION_AP_MASK   (0xFFFF73FF)
#define SECTION_DOMAIN_MASK   (0xFFFFFE1F)
#define SECTION_MASK   (0xFFFFFFFC)
#define SECTION_NG_MASK   (0xFFFDFFFF)
#define section_normal_nc (   descriptor_l1,
  region 
)
#define SECTION_NS_MASK   (0xFFF7FFFF)
#define SECTION_P_MASK   (0xFFFFFDFF)
#define SECTION_S_MASK   (0xFFFEFFFF)
#define SECTION_TEXCB_MASK   (0xFFFF8FF3)
#define SECTION_XN_MASK   (0xFFFFFFEF)

Function Documentation

__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay ( uint32_t  level,
uint32_t  maint 
)
Parameters
[in]levelcache level to be maintained
[in]maint0 - invalidate, 1 - clean, otherwise - invalidate and clean
__STATIC_FORCEINLINE uint8_t __log2_up ( uint32_t  n)
  • log(0) => 0
  • log(1) => 0
  • log(2) => 1
  • log(3) => 2
  • log(4) => 2
  • log(5) => 3 : :
  • log(16) => 4
  • log(32) => 5 : :
    Parameters
    [in]ninput value parameter
    Returns
    log2(n)
__STATIC_INLINE uint32_t GIC_GetConfiguration ( IRQn_Type  IRQn)
Parameters
[in]IRQnInterrupt to acquire the configuration for.
Returns
Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) Bit 1: 0 - level sensitive, 1 - edge triggered
__STATIC_INLINE uint32_t GIC_GetEnableIRQ ( IRQn_Type  IRQn)
Parameters
[in]IRQnThe interrupt to be queried.
Returns
0 - interrupt is not enabled, 1 - interrupt is enabled.
__STATIC_INLINE uint32_t GIC_GetGroup ( IRQn_Type  IRQn)
Parameters
[in]IRQnThe interrupt to be queried.
Returns
0 - Group 0, 1 - Group 1
__STATIC_INLINE uint32_t GIC_GetPendingIRQ ( IRQn_Type  IRQn)
Parameters
[in]IRQnThe interrupt to be queried.
Returns
0 - interrupt is not pending, 1 - interrupt is pendig.
__STATIC_INLINE void GIC_SetConfiguration ( IRQn_Type  IRQn,
uint32_t  int_config 
)
Parameters
[in]IRQnThe interrupt to be configured.
[in]int_configInt_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) Bit 1: 0 - level sensitive, 1 - edge triggered
__STATIC_INLINE void GIC_SetGroup ( IRQn_Type  IRQn,
uint32_t  group 
)
Parameters
[in]IRQnThe interrupt to be queried.
[in]groupInterrupt group number: 0 - Group 0, 1 - Group 1
__STATIC_INLINE uint32_t PTIM_GetEventFlag ( void  )

ref Timer_Type::CONTROL Get the event flag in timers ISR register.

Returns
0 - flag is not set, 1- flag is set
__STATIC_INLINE void PTIM_SetCurrentValue ( uint32_t  value)