CMSIS-Core (Cortex-A)  Version 1.2.0
CMSIS-Core support for Cortex-A processor-based devices
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Reference
Here is a list of all modules:
[detail level 123]
oSystem and Clock ConfigurationFunctions for system and clock setup available in system_device.c
oCore Register AccessFunctions to access the Cortex-A core registers
|oAuxiliary Control Register (ACTLR)The ACTLR provides IMPLEMENTATION DEFINED configuration and control options
||\ACTLR BitsBit position and mask macros
|oCache and branch predictor maintenance operationsThis section describes the cache and branch predictor maintenance operations
|oConfiguration Base Address Register (CBAR)Takes the physical base address value of the memory-mapped SCU peripherals at reset from the external signal PERIPHBASE[31:13]
||\CBAR BitsBit position and mask macros
|oCoprocessor Access Control Register (CPACR)The CPACR controls access to coprocessors CP0 to CP13
||oCPACR BitsBit position and mask macros
||\CPACR CP field valuesValid values for CPACR CP field
|oCurrent Program Status Register (CPSR)The Current Program Status Register (CPSR) holds processor status and control information
||oCPSR BitsBit position and mask macros
||\CPSR M field valuesValid values for CPSR M field
|oData Fault Status Register (DFSR)The DFSR holds status information about the last data fault
||\ACTLR BitsBit position and mask macros
|oDomain Access Control Register (DACR)DACR defines the access permission for each of the sixteen memory domains
||oDACR BitsBit position and mask macros
||\DACR Dn field valuesValid values for DACR Dn field
|oFloating-Point Exception Control register (FPEXC)Provides a global enable for the Advanced SIMD and Floating-point (VFP) Extensions, and indicates how the state of these extensions is recorded
|oFloating-point Status and Control Register (FPSCR)Provides floating-point system status information and control
||\FPSCR BitsBit position and mask macros
|oInstruction Fault Status Register (IFSR)The IFSR holds status information about the last instruction fault
||\IFSR BitsBit position and mask macros
|oInterrupt Status Register (ISR)The ISR shows whether an IRQ, FIQ, or external abort is pending
||\ISR BitsBit position and mask macros
|oMultiprocessor Affinity Register (MPIDR)In a multiprocessor system, the MPIDR provides an additional processor identification mechanism for scheduling purposes, and indicates whether the implementation includes the Multiprocessing Extensions
|oCounter Frequency register (CNTFRQ)Indicates the clock frequency of the system counter
|oPL1 Physical Timer Control register (CNTP_CTL)The control register for the physical timer
|oPL1 Physical Timer Compare Value register (CNTP_CVAL)Holds the 64-bit compare value for the PL1 physical timer
|oPL1 Physical Timer Value register (CNTP_TVAL)Holds the timer value for the PL1 physical timer
|oPL1 Physical Count register (CNTPCT)Holds the 64-bit physical count value
|oStack Pointer (SP/R13)The processor uses SP as a pointer to the active stack
|oSystem Control Register (SCTLR)The SCTLR provides the top level control of the system, including its memory system
||\SCTLR BitsBit position and mask macros
|oTLB maintenance operationsThis section describes the TLB operations that are implemented on all Armv7-A implementations
|oTranslation Table Base Registers (TTBR0/TTBR1)TTBRn holds the base address of translation table n, and information about the memory it occupies
|oVector Base Address Register (VBAR)When high exception vectors are not selected, the VBAR holds the exception base address for exceptions that are not taken to Monitor mode or to Hyp mode
|\Monitor Vector Base Address Register (MVBAR)The MVBAR holds the exception base address for all exceptions that are taken to Monitor mode
oPeripheral AccessNaming conventions and optional features for accessing peripherals
oVersion ControlVersion symbols for CMSIS release specific C/C++ source code
oCore Peripherals
|oGeneric Interrupt Controller FunctionsThe Generic Interrupt Controller Functions grant access to the configuration, control and status registers of the Generic Interrupt Controller (GIC)
|oL1 Cache FunctionsL1 Cache Functions give support to enable, clean and invalidate level 1 instruction and data caches, as well as to enable branch target address cache
|oL2C-310 Cache Controller FunctionsL2C-310 Cache Controller gives access to functions for level 2 cache maintenance.
Reference: Level 2 Cache Controller L2C-310 Technical Reference Manual
|oGeneric Physical Timer FunctionsGeneric Physical Timer Functions allow to control privilege level 1 physical timer registers on Generic Timer for Cortex-A7 class devices.
Reference: Cortex-A7 MPCore Technical Reference Manual
|oPrivate Timer FunctionsPrivate Timer Functions controls private timer registers present on Cortex-A5 and A9 class devices.
References: Cortex-A5 MPCore Technical Reference Manual, Cortex-A9 MPCore Technical Reference Manual
|oMemory Management Unit FunctionsMMU Functions provide control of the Memory Management Unit using translation tables and attributes of different regions of the physical memory map.
Reference: Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition
||\MMU Defines and StructsDefines and structures that relate to the Memory Management Unit
|\Floating Point Unit FunctionsFPU Functions enable the use of Floating Point instructions and extensions.
Reference: Architecture Reference Manual Reference Manual - Armv7-A and Armv7-R edition
oCompiler ControlCompiler agnostic #define symbols for generic C/C++ source code
oIntrinsic FunctionsFunctions that generate specific Cortex-A CPU Instructions
\Interrupts and ExceptionsGeneric functions to access the Interrupt Controller
 oIRQ Mode Bit-MasksConfigure interrupt line mode
 \IRQ Priority Bit-MasksDefinitions used by interrupt priority functions