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IENABLE and IDISABLE giving errorin RVCT

Dear all, I am using LPC 2132 controller. In nested interrupt IENABLE and IDISABLE macros giving error in RVCT.
The error is as below

source\cpu.c(61): error:  #20: identifier "LR" is undefined
source\cpu.c(61): error:  #20: identifier "SP" is undefined
source\cpu.c(61): error:  #20: identifier "LR" is undefined
source\cpu.c(61): warning:  #1287-D: LDM/STM instruction may be expanded
source\cpu.c(61): error:  #20: identifier "SP" is undefined
source\cpu.c(61): error:  #20: identifier "LR" is undefined
source\cpu.c(61): error:  #29: expected an expression


Can any body suggest the problem in my project settings. The same function and same macro is working in CARM. Regards S Rajan