IENABLE and IDISABLE giving errorin RVCT

 IENABLE and IDISABLE giving errorin RVCT

Dear all, I am using LPC 2132 controller. In nested interrupt IENABLE and IDISABLE macros giving error in RVCT.
The error is as below

source\cpu.c(61): error:  #20: identifier "LR" is undefined
source\cpu.c(61): error:  #20: identifier "SP" is undefined
source\cpu.c(61): error:  #20: identifier "LR" is undefined
source\cpu.c(61): warning:  #1287-D: LDM/STM instruction may be expanded
source\cpu.c(61): error:  #20: identifier "SP" is undefined
source\cpu.c(61): error:  #20: identifier "LR" is undefined
source\cpu.c(61): error:  #29: expected an expression

Can any body suggest the problem in my project settings. The same function and same macro is working in CARM. Regards S Rajan

 RE: IENABLE and IDISABLE giving errorin RVCT

You can't use those macros in RVCT.

 RE: IENABLE and IDISABLE giving errorin RVCT

Then how can i use nested interrupt in RVCT.
S Rajan

 RE: IENABLE and IDISABLE giving errorin RVCT

You have to write it in an assembly module

 RE: IENABLE and IDISABLE giving errorin RVCT

See: http://www.keil.com/support/docs/3229.htm