Hello everybody,
Quoted from the user manual of LPC178: " The on-chip flash memory is not accessible during erase/write operations. When the user application code starts executing the interrupt vectors from the user flash area are active. The user should either disable interrupts, or ensure that user interrupt vectors are active in RAM and that the interrupt handlers reside in RAM, before making a flash erase/write IAP call. The IAP code does not use or disable interrupts."
I do not completely understand the purpose of this paragraph. Is it enough to disable interrupts using __disable_irq() function before starting to use IAP? And how can "I ensure that interrupt vectors are active in RAM" ?
Thank you all for helping
The key thing to understand is that a flash array is generally unreadable while an erase/write is occurring, instead returning status information. A processor attempting to fetch/execute/read such memory is going to crash, or at the very least load invaliding information.
Fetching interrupt vectors will also fail. Disabling interrupts will stop maskable interrupts, but not things like NMI, or Hard Fault, etc
The Cortex-M3 permits the vector table to be moved via the SCB->VTOR register, RAM is nominally at 0x20000000, you could copy your vector table there. Your specifc chip may also permit RAM, ROM or FLASH to be mapped (shadowed/mirrored) at address 0x00000000.
When flashing it's often desirable to create a small app (group of routines) that can be copied to RAM in a free standing fashion and executed there. If you can write a small IAP boot loader that fits in 16KB, as it's own Keil project, that could be stored in FLASH, and then copied to RAM and jumped too.
Having your application running all kinds of interrupts, and peripherals, is not conducive to performing a safe flash update.
thanks a lot Westonsupermare Pier
It really helped. I will try what you have just suggested. If I have any problems, I will be back asking more questions.