Can an interrupt of higher natural priority interrupt one of lower priority? For the time being my question is limited to the case where none of the interrupts' priorities are promoted in the IP. I'm using the Dallas DS80C320 part. I have tried a variety of hardware experiments which suggest that a higher natural priority interrupt CANNOT interrupt one of lower priority but these experiments have not been conclusive (i.e. I have not seen a higher priority event interrupt a lower priority event on my emulator). From what I've observed it seems that the priority scheme only affects which interrupt runs first if both occur during the same machine cycle. In that case both run sequentially, higher priority first, returning to execute one line of code, then second priority. However I'm not entirely confident that I've covered all the possible use cases. I have not been able to get a straight answer from the part vendor (Dallas). They have suggested that the LJMP from the interrupt event to the ISR vector can itself be interrupted. This seems wrong. The reason for this question is that I've ported the uC/OS multi-tasking operating system to my part and I've experienced some intermittent problems when external interrupts are introduced into the system. The OS relies on a CPU context dump to XDATA being performed upon entry into an ISR and this sequence cannot be interrupted, hence my question. I'd appreciate input from anyone with more experience on this part or with '51 interrupts in general. Thanks in advance, Chip Burns
On the 8051, a higher priority interrupt CAN interrupt a lower priority interrupt IF interrupts are enabled. If you have a low priority interrupt that you do not wish to be interrupted, you CAN disable all interrupts. Jon
Hi, A low priority interrupt can be interrupted by a high priority interrupt BUT this is acheived by setting it to high priority in the Interrupt priority (IP) register. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority is serviced. If two interrupts of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. The interrupt polling sequence (from highest to lowest) is:- INT0 TF0 INT1 TF1 RI and TI This is for the 8051 and taken from a Philips data book!. I think that after the interrupt system generates an LCALL to the appropriate vector it cannot be interrupted unless you have set some to be of higher priority in the IP register. Hope this helps, Mark.
Making the distinction between IP-configured priorities and "natural" priorities (i.e., hardware-assigned priorities within an IP-configured priority level), in a single level priority system like you describe, my experience is consistent with your observations and that the vectoring LJMP (LCALL, actually) will not be interrupted in this situation. Multiple level priority systems operate per Jon's comments and in these cases, the LCALL can be interrupted like Dallas says. Perhaps Dallas misunderstood the nuance of your question???
Thanks to all who have responded. To clarify my case: IP = 0 Sequence: 1 - <falling edge trigger on /INT0 pin> 2 - LCALL 0x0003 (CPU generated call) 3 - CLR EA (my code) 4 - ... context dump ... From what I've read so far it seems that line 3 is not even required. Any opinions? Thanks again, Chip Burns
Sorry, should have shown /INT1 for obvious reasons
Hi, Correct, line 3(CLR EA) is as you say not needed, although I can't see any harm in leaving it in unless you perhaps intend using higher priorities can interrupt later? Mark.
This is very well described in the '51 'bible'. At http://www.8052.com/links.phtml under "intersting sites" you will find links to chapters 1, 2 and 3 of the '51 "bible". Erik