The SSP peripheral of my LPC2478 (configured to use SPI frames) is generating a "RNE equals 1" status (Receiver Not Empty - thus, there is data available in the RX FIFO) after some data is placed in the data register to be sent out (I am sure no data has actually been received from the slave). I cannot find an explanation for this - however, I must add that I am using a temporary test rig (until the real hardware is available) that might suffer from EMC issues, and that if I slowly run the code using a debugger this does not seem to occur. I did not find any indication in the user manual that such behavior can be expected, but some guy at NXP told me that "When the transmission is over, it is expected that the receive channel also contains data. " (there has been no further advise from them). Does this make sense to you? All in all it is working, and I can sustain a transfer rate of over 36 KB/sec in a (still) non-preemptive environment, but this does not seem right, so I was hoping you can share your thoughts with me.
I got this reply from NXP:
"The SSP/SPI works like a "shift register". While sending a frame (MOSI) data is shifted out, but at the same time data is shifted in from the MISO line. Normally this data comes from the slave, but if nothing is connected to this line all FF or 00 will be received."
Sounds pretty normal to me.
But I do not use the MISO pin at all - it is configured as GPIO (I know I should have mentioned that - I only use MOSI). Is it still pretty normal...?
Yes its normal.
External is not connnected does not mean that the internal logic is not functional.
That makes sense - after all, it is no more than a shift register.
The thread is old but I'll comment anyway.
The trivial implementation of SPI is just a single shift register without any buffering at all. Just as many bits are shifted in as are shifted out.
On top of this, you may then have a single read and/or write buffer or full FIFO support.
But the special thing with SPI is that it is always two-way. The same number of bytes sent and received, even if real data is only sent in one direction.
That also means that if having multiple slaves connected to a single master, it is possible to write to all slaves at the same time. But then the MISO lines must not be connected, or the slaves (at least all but one) have to disable their output signal to avoid generating a collision.
In the end, you have a pin multiplexer allowing the processor pins to be GPIO or different special functions. But there is no disable for the internal logical function. Your UARTs, SPI etc will continue to try to work even if you don't map the signals to real pins. In some situations, that is ok. In other situations, the operation of the device will not be meaningful without mapping one or more signals to real physical pins.
Thanks Per. In the system I'm working on now, each peer that wants to send data takes the role of the SPI bus master (don't worry: there is role arbitration using 2 GPIO pins), so that I don't have to generate the clock pulses for the slave by dummy writes/reads at the master - replies could be quite long and that is not possible to sustain in a preemptive environment anyway (unless you really jump through the hoops!). So there a data transfer protocol underneath which dictates who the physical bus master actually is (a role that is exchanged between the peers), but the "logical master" does not - the logical master is the peer that initiated the entire transaction (the logical slave can only reply with a NACK or ACK). This may be slightly limited by greatly simplifies the protocol.