Hi: I have read one of the app note that keil provided "in-system flash programming" (http://www.keil.com/support/docs/2364.htm) and became confused. In my opinion, the uC core can only fetch instruction from rom or flash. But as the app note said, the code can be execuated in ram(using srom class). The way of copy the code from flash to ram can be easily understand, but how can it execuate there. In my opinion, the process of how to fetch instruction is only decided by the core construction, but not the complier or linker tools. what is the real instruction fetch mechanism about 51MCU. Is there any document related ? I do not know search what key point for this question. Thaks for your help.
aaa1982
The way of copy the code from flash to ram can be easily understand, but how can it execuate there.
If RAM is mapped into code space, code can be executed from there. There's no difference for the MCU.
However, there needs to be a mechanism for copying the code to the RAM, since the 8051 does not have any instructions that write to code space. This can be accomplished, for example, by mapping the same RAM into the XRAM space, or by using SFRs to access this RAM.
hi Christoph: Thanks for your replying. If RAM is mapped into code space, code can be executed from there. There's no difference for the MCU. I want to know how to map the RAM into the CODE space and if all of the MCU(such as C8051F series)support memory mapped? In other words, if I want to map the ram into code space, what MCU should I　used?
Jason liu
I want to know how to map the RAM into the CODE space simple use a negative OR (same as a positive AND) of !PSEN and !RD to read the RAM. and if all of the MCU(such as C8051F series)support memory mapped? Memory mapped I/O (the usual meaning of 'memory mapped'), yes, but I do not think that is what you mean In other words, if I want to map the ram into code space, what MCU should I used? Any derivative with the ability to use external code memory (no C8051F (assuming you refer to SILabs) can)
Erik
PS WHY do you want to do this?
As Erik says, for external RAM, it is simply a matter of implementing the appropriate logic in your memory interface so that accesses to CODE space can be directed to the RAM.
For internal RAM, it depends entirely on the specific chip in question - but I suspect that this is quite rare?
Thanks Erik and Andrew:
In my opinion,if the ram have enough space,it can reduce power consumption when CPU fetch instruction from ram rather than from flash. Becasue from the datasheet , the core power consumption with flash operation is aways higher than it without flash operation. Is it an accurate idear?
Thanks for your help
Jason
... where you can depower the internal flash
The ARM chips LPC23xx can depower the flash, but only in deep sleep mode, so it will not run any code in RAM either.
I think you really have to search for a microcontroller that can turn off the power to the internal flash while running from RAM.
"it can reduce power consumption when CPU fetch instruction from ram rather than from flash. Becasue from the datasheet , the core power consumption with flash operation is aways higher than it without flash operation. Is it an accurate idea?"
It is impossible to say whether or not this is accurate as it is entirely dependent on the specific chip in question - an essential detail which you have omitted to even hint at!
But I suspect that it is not accurate:
I suspect that you are trying to add apples to pears and get oranges!
Usually, chips have more flash than RAM - often much more. So, if you use up all your RAM to hold the code, where will your data go...?
It is plausible that executing from ram would have reduced power consumption, again depending on the specific chip.
Memory access times to an internal ram are typically a lot faster than access times to an internal flash. Wait states need to be inserted in some cases when fetching instructions and data from an internal flash above a certain core frequency. The power requirements are higher therefore because it takes longer to perform the same task from flash than it would from RAM.
At least for simple microcontrollers with flash and ram, the flash and ram take a significant portion of the silicon area and so are major consumers of the power used by a chip during its operation. The flash and ram ip used in a particular part would have specifications for the power requirements for a read operation (as well as a program or erase operation). If this figure is higher for the flash (I'd assume that it was), then executing from ram would reduce your power consumption.
"The flash and ram ip used in a particular part would have specifications for the power requirements for a read operation (as well as a program or erase operation). If this figure is higher for the flash (I'd assume that it was), then executing from ram would reduce your power consumption."
Then again, the flash is - I think - usually bigger; so it would be expected to take more power. If the RAM were increased to the same size as the flash, it would probably take more power...
Thanks all above:
I once read some MCU datasheet and find the difference between normal mode and idle mode is whether the CPU is active. In normal mode,cpu is active fetch instruction from flash,while in idle mode,cpu is inactive and not fetch instruction form flash
So I soppose that when the CPU is active ant not fetch instruction from flash. The power consumption will between the normal mode and idle mode.
"I once read some MCU datasheet"
You are asking questions that rely upon specific details about specific chips - you cannot just rely on vague recollections on unspecified documentation!
You need to carefully study the specific datasheet for the specific chip in question.
"So I suppose that when the CPU is active ant not fetch instruction from flash..."
No, you can't just "suppose" that - you need to study the specific datasheet for the specific chip in question and see precisely what it says about the matter.
But, surely, the very definition of "Active" means that the CPU is fetching (and executing) instructions - so it cannot possibly be "active" and yet not fetching instructions?!
Again, terms like "idle", "sleep", and "active" will have specific definitions for the particular chip can only be found by studying the specific datasheet for the specific chip.
In summary: stop guessing; start studying.
Hi Andy:
Take C8051F3xx for example. Look at the Global Electrical Characteristics at P28 of the datasheet(c8051f320).
CPU Active (Normal Mode, fetching instructions from Flash) VDD = 3.3 V, F = 24 MHz Typical current=10.6mA CPU Inactive (Idle Mode, not fetching instructions from Flash) VDD = 3.3 V, F = 24 MHz Typical current=5.2mA
I just want to know , when I use an external ram (C8051f320 do not support but c8051f340 support).If it can copy the code from flash to ram at beginning and run the code at ram. If it can working, whether it will save power versus fetch the instruction from flash.
Now it is an actual question rely on an specific MCU(c8051f340).
Thanks for your replying
"If it can copy the code from flash to ram"
Remember: the CPU knows nothing about "flash" or "RAM" - all it knows about is CODE and XDATA address spaces.
The CPU can only ever fetch instructions from CODE space - so you need to check the Datasheet to see if this chip has any facility to map CODE space onto the external RAM.
"If it can working, whether it will save power versus fetch the instruction from flash."
Only the specific Datasheet can tell you that.
It seems unlikely unless this chip gives you some facility to power-down the Flash when you're not using it - again, only the specific Datasheet can tell you that.
These are chip-specific hardware details; nothing to do with the Keil software tools. For detailed chip-specific questions like this, you need to be talking to the Chip Manufacturer - ie, Silicon Labs - not the software tool vendor (Keil).
What does "Idle Mode" mean...?