AT91SAM9260 and ADS1278 - Random AQ array position

Hallo,

I'm using AT91SAM9160's SSC interface in Frame-Sync mode in order to interface an ADS1278 (24-bit ) converter operating in TDM fixed-mode ( All eight AD channels will be sent over DOUT1 pin one after the other ) doing max 128kSPS.

The ADS1278 is continuously receiving SCLK, CLK and FSYNC signals.
I'm using RK0 to provide SCLK and CLK, RF0 to provide FSYNC and RD0 to collect ADC data via DOUT1.

The problem I'm experiencing is related to the ADC channel information sequence that is being placed in memory buffer by PDC (DMA). The information seens to be out of sync, if I put the maximum positive value at the first channel CH1, leave all the other seven channels floating, and do several convertions, I can see that conversion value from CH1 will be put at random array's position. No data is lost though, all eight channels are converted correctly. This behavior can be noticed by using any CH1-CH8 or even in pars CH1 and CH2, CH1 and CH8.

ex.:
U32 adc_raw1[BUF_SIZE]; /* ADC buffer used by DMA */

1st) eight channel aquisition run, CH1 will be placed at:

adc_raw[0]=
0x007FFFFF

2nd) run:
adc_raw[6]=
0x007FFFFF

3rd) run:
adc_raw[4]=
0x007FFFFF

4th) run:
adc_raw[2]=
0x007FFFFF

Checking with a Scope I can see that the ADC channel sequence is correct.
The information is comming out of the ADS in a correct sequence.
CH1 CH2 CH3 CH4 CH5 CH6 CH7 Ch8 ( MSB First )...

Have anyone experienced similar problem?

Bellow is a piece showing my configuration parameters:

/*--------------------------------------------------------------------
    Configuration parameters for ADS1278 interface via SSC frame_sync
--------------------------------------------------------------------*/
#define MCK             96109714    /* Main clock frequency in Hz  */
#define SAMPLE_FREQ     25000
#define HIGH_SPEED      256   /* fCLK/fDATA = 256*/
#define SLOT_BY_FRAME   8     /* Number of ADC CHannels */
#define BITS_BY_SLOT    24
/*--------------------------------------------------------------------
    Config dos resistros de hardware
--------------------------------------------------------------------*/
#define PERIOD                      ((U32)(((SLOT_BY_FRAME*BITS_BY_SLOT)/2)-1) << 24)
#define CKS_DIVIDED_CLOCK           ((U32)0<<0)
#define CKO_CONTINUOUS              ((U32)1<<2)
#define CKO_ONLY_ON_DATA_TRANSFER   ((U32)2<<2)
#define CKI_SAMPLE_FALLING_EDGE     ((U32)0<<5)
#define CKG_NO_CLOCK_GATE           ((U32)0<<6)
#define STOP_RX                     ((U32)0<<12)
#define RFMR_DATLEN                 ((U32)(BITS_BY_SLOT-1)<<0)
#define RFMR_LOOP                   ((U32)0<<5)
#define RFMR_MSBF                   ((U32)1<<7)
#define RFMR_DATNB                  ((U32)(SLOT_BY_FRAME-1)<<8)
#define RFMR_FSLEN                  ((U32)0<<16)
#define RFMR_FSOS                   ((U32)2<<20)
#define RFMR_FSEDGE                 ((U32)0<<24)
/*--------------------------------------------------------------------
        Buffer de recepcao de dados do ADS1278
--------------------------------------------------------------------*/
#define ADS_UMA_AMOSTRA 8
#define ADS_N_AMOSTRAS  1
#define BUF_SIZE ( ADS_UMA_AMOSTRA*ADS_N_AMOSTRAS )
U32 adc_raw1[BUF_SIZE]; /* ADC buffer used by DMA */
U32 adc_raw2[BUF_SIZE];

/*--------------------------------------------------------------------
--------------------------------------------------------------------*/
void SSC_Configura ( void )
{
    AT91F_SSC0_CfgPIO   ();
    AT91F_PIO_CfgPullup (AT91C_BASE_PIOB, AT91C_PB20_RK0);
    AT91F_SSC0_CfgPMC   ();
    AT91C_BASE_SSC0->SSC_CR = AT91C_SSC_SWRST;
    AT91F_PDC_Close((AT91PS_PDC) &(AT91C_BASE_SSC0->SSC_RPR));

    AT91F_SSC_SetBaudrate ( AT91C_BASE_SSC0, MCK, SAMPLE_FREQ * HIGH_SPEED );

    /* Confige for ADS1278 frame-sync */
    AT91C_BASE_SSC0->SSC_RCMR = (   (( CKS_DIVIDED_CLOCK)& AT91C_SSC_CKS) |
                                    (( CKO_CONTINUOUS)& AT91C_SSC_CKO) |
                                    (( CKI_SAMPLE_FALLING_EDGE)& AT91C_SSC_CKI) |
                                    (( CKG_NO_CLOCK_GATE)& ((U32) 0x3 <<  6)) |
                                    (( AT91C_SSC_START_RISE_RF)& AT91C_SSC_START) |
(( STOP_RX)& AT91C_SSC_STOP) |
                                    (( PERIOD)& AT91C_SSC_PERIOD)
                                );
    AT91C_BASE_SSC0->SSC_RFMR = (   ((RFMR_DATLEN)& AT91C_SSC_DATLEN) |
                                    ((RFMR_LOOP)& AT91C_SSC_LOOP) |
                                    ((RFMR_MSBF)& AT91C_SSC_MSBF) |
                                    ((RFMR_DATNB)& AT91C_SSC_DATNB) |
                                    ((RFMR_FSLEN)& AT91C_SSC_FSLEN) |
                                    ((RFMR_FSOS)& AT91C_SSC_FSOS)
                                );
/*--------------------------------------------------------------------
    Enable DMA transfer
--------------------------------------------------------------------*/
    AT91F_PDC_SetRx     ( AT91C_BASE_PDC_SSC0,(S8*)adc_raw1, BUF_SIZE);
    AT91F_PDC_SetNextRx ( AT91C_BASE_PDC_SSC0,(S8*)adc_raw2, BUF_SIZE);
    AT91F_PDC_EnableRx (AT91C_BASE_PDC_SSC0);   /* Enable the PDC feature */
    AT91F_SSC_EnableRx ( AT91C_BASE_SSC0 );
}
/*--------------------------------------------------------------------
--------------------------------------------------------------------*/
int main ( void )
{

    SSC_Configura();

        while(1)
        {
               AT91F_SSC_ReceiveFrame (AT91C_BASE_SSC0, (S8*)adc_raw1, BUF_SIZE, (S8*)adc_raw2, BUF_SIZE);
        }
}
/*--------------------------------------------------------------------
--------------------------------------------------------------------*/

the *pre* and */pre* tags doesnt seens to be working right...
Any help would be much appreciated.
Alex