Hi, I poll an i2c device every 250[ms] without any runtime issues, but sometimes I see that if I reset the MCU using the debugger while this polling takes place (thus without a power cycle) the busy bit of my i2c peripheral remains active, which prevents i2c devices configuration during the next startup. The data sheet of the STM32F4 says that the busy bit is enabled if either SCL or SDA are driven low which is indeed the case (I measure with a scope). My question is: is it possible that SCL or SDA remain driven my the i2c device because of the abrupt reset of the MCU occured while the device was communicating? I use poll up resistors. Thanks in advance.
"It is generally known that the I2C bus can hang if an I2C master is removed from the bus in the middle of a data read. This can occur because the I2C protocol does not mandate a minimum clock rate. Therefore, if a master is reset in the middle of a read while a slave is driving the data line low, the slave will continue driving the data line low while it waits for the next clock edge. This prevents bus masters from initiating transfers. If this condition is detected, the following three steps will clear the bus hang condition: 1. An I2C master must generate up to 9 clock cycles. 2. After each clock cycle, the data pin must be observed to determine whether it has gone high while the clock is high. 3. As soon as the data pin is observed high, the master can initiate a start condition."
See here: www.ti.com/.../sprz335h.pdf