LPC2378 CCLK Switching to 72Mhz Error

Hi,
I was trying to configure PLL and other clocks for LPC2378.While setting the processor clock to 72 MHz(Max CCLK as per the User manual), the code stuck's.The code goes like this, after setting System Controls and Status register(init_SCSRegister() function) it goes for the init_PLL_CLOCKS() function. The code get's suck at CCLKCFG=0x03, as iam using 12 Mhz external crystal and PLL configured to 288Mhx expected CCLK = 288/4 = 72Mhz. For other Lower CCLk's(Like 48 Mhz(CCLKCFG=0x05)) its working fine .

Hardware Details

Custom Board
Controller- LPC2378 Revision D
External Osc - 12Mhz
IDE Keil micro vision 3

void init_SCSRegister(void){
        SCS|=(BASE_VALUE<<GPIOM);      // Setting the GPIOM Bit
        SCS&=~(BASE_VALUE<<MCIPWR);
        SCS&=~(BASE_VALUE<<OSCRANGE);  // Clearing the Osc range bit(External Crystal 12Mhz)
        SCS|=(BASE_VALUE<<OSCEN);      // Enabling External Oscillator
        while(!(SCS&(BASE_VALUE<<OSCSTAT))); // Waiting for the Oscillator to stabilize
}



void init_PLL_CLOCKS(void){


        if(PLLSTAT&(BASE_VALUE<<PLLC_Status)){
        PLLCON&=~(0x01<<PLLC);// Disconnect PLL if already connected
        feed_PLL();             // PLL Feed Sequence
        }
        PLLCON=0x00;            // Disable PLL
        feed_PLL();             // PLL Feed Sequence

        CLKSRCSEL=0x01;         // Selects the main oscillator as the PLL clock source.
        PLLCFG = ((1<<NSEL)|(47<<MSEL));// Switching PLL to 288MHz(12Mhz x 48 /2 )
        feed_PLL();             // PLL Feed Sequence

        PLLCON=0x01;            // Enable PLL
        feed_PLL();             // PLL Feed Sequence
        CCLKCFG=0x03 ;          // Setting processor clock(CCLK) to 72 Mhz(288/4)
        USBCLKCFG=0x05;         // Setting USB clock to 48Mhz(288/6)
        PCLKSEL0=0;             // Setting to default clock divider for peripheral(CCLK/4)
        PCLKSEL1=0;             // Setting to default clock divider for peripheral(CCLK/4)
        while( !( PLLSTAT & (BASE_VALUE<<PLOCK_Status))); //Wait until PLL get's locked

        PLLCON|=(0x01<<PLLC);  //Connect PLL
        feed_PLL();             // PLL Feed Sequence

}


void feed_PLL(void){
        PLLFEED = 0xAA;
        PLLFEED = 0x55;
}

Will it be due to error/Tolerance with external crystal?? or doesn't this chip/version cant be switched to 72Mhz CCLK??

Please add your comments.

Thank You