I am using the CMSIS RTOS (not RTX) and this RTOS seems to be interfering with a time critical process I have for programming a FPGA so I need to suspend this RTOs until I am finished doing that.
In RTX I could call os_suspend. I have implemented this same call with CMSIS RTOS and it does not seem to do anything. Threads are still functioning as well as mailboxes timers etc.
How can I suspend the CMSIS RTOS?
There is no documenation anywhere about this
See this application note
http://www.keil.com/appnotes/files/apnt_264.pdf
The last page it shows that the suspemd function is not implemented. And suggests using a SVC call instead.
Thanks for the information.
Keil tech support also just got back to me and said to try calling osKernelinitialize() to stop any scheduler events as long as I did not make a system wait call.
That idea did not help. Because the microsemi cortex m3 does a flash freeze I cannot use the debugger at all so this turns into a black box to me once the ISP FPGA reprogramming begins.
I know my code works because before integrating with the RTOS I was able to run my system and successfull run this code out of esram and get the FPGA programmed
With the lurking the the background I cannot get this code to successfully program the FPGA. It starts but something happens (black box) that is causing it to fail.
I am assuming it may be a contex switch by the RTOS, a RTOS timer tick interrupt, or something like that which takes control away from the code running in the esram and then it all falls apart.
This is a unusual situation but the way that microsemi design this to work I am stuck trying to get it to work. They only tested it stand alone so did not see problems like this coming.
Any additional ideas or sugguestion about how to get the RTOS to leave me alone while doing this programming?
After programming, my code in nvm is overwritten which is why I must run out of esram. Life boat. So this reprogramming process will never return so I don't care if the RTOS is restarted
Disabling all interrupts can normally also help leaving the processor focused on a single problem until the interrupts are enabled again.
I have seen a couple of different ways to do the disabling of M3 interrupts. What would you recommend as the safest/best way to disable interrupts?
method 1
__set_BASEPRI(6 << (8 - __NVIC_PRIO_BITS));
method 2
void core_critical_enter(void) { __disable_irq(); ++lock_nesting_count; }
void core_critical_exit(void) { /* Unlock interrupts only when we are exiting the outermost nested call. */ --lock_nesting_count; if (lock_nesting_count == 0) { __enable_irq(); }
And here is a 3 method that does a more sophisticated way of handling nested critical sections (which I do not have).
static inline uint32_t sl_hw_lock(void) __attribute__((always_inline, unused)); static inline void sl_hw_unlock(uint32_t primask) __attribute__((always_inline, unused));
/** * Lock interrupts to start a critical section. * * When used with sl_hw_unlock() this function starts a critical section that * works properly even if nested in another critical section because it reads * the PRIMASK value so it can be restored. * * @return the priority mask (PRIMASK) register value upon entry */ static inline uint32_t sl_hw_lock(void) { uint32_t primask;
asm volatile("mrs %0, primask\n" : "=r" (primask)::); __disable_irq(); return primask; }
/** * Unlock interrupts to end a critical section. * * When used with sl_hw_lock() this function ends a critical section that works * properly even if nested in another critical section because it uses the * previous interrupt locking state (defined by PRIMASK) to selectively unlock * interrupts. * * @param primask The previous priority mask (PRIMASK) register value as * returned by sl_hw_lock(). */ static inline void sl_hw_unlock(uint32_t primask) { if (primask == 0) { __enable_irq(); } }