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Maybe some1 can help with next questions: - are dominant bits produced with zeros? For example, if CANIDTx register contain 11110000 so does CAN transmit r-r-r-r-d-d-d-d bits (r=recessive, d=dominant)? Here we connect CAN RX/TX directly to 82С250 chip. - which order of transmitted bits? Is it next: bit 7 of CANIDT1 ... bit 0 of CANIDT1 ... bit 3 of CANIDT4 (with service bits inside, ofcoz)? - is it necessary to set CANIDMx registers for transmit message objects? Why? - does CAN controller of T89C51CC01 retransmit frames if it detects BERR (Bit error)? And AERR (Acknowledgement error)? Or does it set corresponded bit only and it is my task to retransmit it again? - What is difference between General Errors (bits of CANGIT register) and Message Object Errors (bits of CANSTCH register)? - does CANIT bit work only if CAN interrupts are allowed by set ECAN set? Thanks you, I have even more questions next time (= Good days!