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ARM: STR91x interrupt handling problem (cont)

Responding in new thread since other thread is dead.
http://www.keil.com/forum/21199

So, anyone else with this problem?
It seems to be a general Keil issue...

Anyone else with what problem? Forgetting to use the correct keyword to tag an ISR as an ISR?

What general Keil issue? That the compiler needs to adapt to the hardware?

Lots of compilers for lots of processors have needed a special keyword to let the compiler know when it should generate prologue/epilogue for an ISR instead of for a normal function.

A number of processors have a normal "RET" instruction and a special "RETI" instruction.
Or need to name specific registers to reload PC with the correct return address depending on if the processor did use the normal stack or an interrupt stack.

And an ISR often need to save extra registers compared to a normal function, since the interrupt can happen asynchronously - breaking in in the middle of other code execution.

So if you Google and finds lots of mentions of Keil, it is just because Keil works with compilers for embedded use. So the majority of users of Keil tools will create interrupt handlers.

Only OS or drive routine coders need to care about any interrupt handlers if you write code for a modern PC. So you don't see lots of threads about interrupt handlers for Visual C++.

Of course - a processor can be implemented in a way where an ISR do not need any special prologue or epilogue. In that case, there will be no need for any extra keyword to tag the ISR as different from a normal function. ARM did add extra logic in the Cortex chips to allow 100% of the code to be written in C, and without any special keyword for ISR. But that is an exception to the rule that interrupt service routines are different from normal functions.