problem in pll settings

 problem in pll settings

hello
I am currently working on a project which has 20 Mhz osc.
I am using LPC2368
I want CCLK should me 48Mhz
Can anybody please explain me configuration required for pll registers.
I have gone through NXP exel sheet according to that for my application
M value is 12
N value is 1
Fcco value is 480

but when I make this changes I was not getting CCLK as 48MHz

Please Help!

 RE: problem in pll settings

So what did you get?

And are you sure you do have a 20MHz oscillator?

And are you using the configuration wizard? If not - have you taken into account that the PLLCFG register should be configured with M-1?

 RE: problem in pll settings

Thank for reply

Yup I am sure I am using 20MHz crystal
N i dia M-1=12-1=11=B
so i did according settings in PLLCFG

Is it necessary that Input clock frq(20Mhz) should completely divide CCLk?

 RE: problem in pll settings

No - 20MHz crystal should give perfect generation of 48MHz using a large number of PLL combinations.

What processor stepping do you have?

The original '-' stepping can't support an intermediate frequency as high as 480MHz. The errata gives a limit of max 290MHz for Fcco. But that is ancient silicon.