Address Space overflow

I am using 8051F120 having 127KB Program memory, theoretically. I have written 4 *.C files residing in each bank. The length of the code in Bank1 and Bank2 is less than 32KB (observing the list file). But, instead of this, the linker gives an address space overflow for both the banks.
Kindly assist.

Dhaval Solanki

 RE: Address Space overflow

Did you checked this app.note from Silabs? It's all there...

http://www.silabs.com/Support%20Documents/TechnicalDocs/an130.pdf

- Dejan

 Why bother with Banking?

You are struggling with Banking - why?

Banking is just a bodge to get around a fundamental limitation of an architecture.
It only made sense when a move up to an architecture without that limitation was out of the question.

Nowadays, architectures without that limitation are widely available and easily accessible - so why mess with Banking?

Even SiLabs - that bastion of high-end 8051 - now has ARM Cottex-M3 chips available...

 RE: Why bother with Banking?

Surely the OP answered that one by saying I am using 8051F120...

Looks like you're misinterpreting the am using as being intend to use.

As a consultant, I have frequently been given platforms to write code for that I would prefer to exist on (what I consider to be) a better platform.

 RE: Looks like you're misinterpreting the am using as being intend to use.

No, I'm saying, "why are you using that platform?"

The post does not give the impression that the OP is an expert on that platform, so the cost of switching may not be high - in particular, not higher than trying to master Banking...

"As a consultant..."

Well, of course, the customer is always right; if they're prepared to pay over the odds due to a sub-optimal platform choice - that's their choice.

Doesn't stop you voicing your opinion that there may be A Better Way, though - does it?

 Experience

Doesn't stop you voicing your opinion that there may be A Better Way, though - does it?

IMO, one sure fire way of alienating a development department who may have spent a lot of time really understanding a situation is for a consultant new to the task to come in and say "you're bodging it" and "I wouldn't do it that way".

 RE: Experience

There are always ways to alienating yourself. But being silent instead of bringing up potential issues just means they pay for a consultant that doesn't deliver the full knowledge/experience.

While it is obviously not a good idea to cut someone at the knees by asking who was the fool to select a specific processor, there are lots of ways to point out the potential problems with the selected route and wonder if alternative routes - such as using a (similarly priced) processor with a large linear address space - would be an option to speed up the total development times and cut problem complexity.

Many times, people just don't realize the implications of having a processor with 256kB of flash but an adressing scheme that requires only a small part of that flash to be visible at any one time. Datasheets for the processor (or application notes) will obviously not spend time describing the issues with the processor. At best, the application note will describe the availability of code banking - making it sound like a nice feature of the processor instead of a cludge to work around a huge design issue.

 Diplomacy

There are always ways to alienating yourself. But being silent instead of bringing up potential issues just means they pay for a consultant that doesn't deliver the full knowledge/experience.

Certainly can't dispute that.

I've witnessed it from both sides; and admit to being really ticked off in one situation where the management recruited a "sharp-as-a-knife consultant" who caused a product to be redesigned very late in the day because what we'd done was "so Heath Robinson" and should be chucked out.

The expert consultant really didn't understand what we'd done and why. He had pre-conceived ideas from which he would not deviate and he would not listen to technical or cost arguments. But the management liked him because he was oh so decisive.

Long story short, the expert consultant failed in his task, he was kicked out, our work was resurrected and the project was successfully completed.

 RE: Experience

But this is not a cunsultancy session - this is a discussion forum.

If the OP wants to engage in the discussion, he could explain why the bodge is necessary or appropriate in his particular case.

I am open to be persuaded...

 Advice

To the OP.

Without further details it's hard to determine what might be wrong. You need to check the banking parameters (especially start, size etc).

 Simple etiquette

If the OP wants to engage in the discussion, he could explain why the bodge is necessary or appropriate in his particular case.

You, I and nobody apart from the OP (and his team) knows whether it is necessary and/or appropriate to use banking at this time. Until such time, it would be better to avoid looking excessively arrogant and assume it might not be a bodge.

 RE: assume it might not be a bodge.

Experience of this and other forums suggests that is quite possibly not a valid assumption.

http://www.catb.org/~esr/faqs/smart-questions.html#goal

 RE: Why bother with Banking?

Surely the OP answered that one by saying I am using 8051F120...

No, he didn't. That's stating a fact, but no reason for why that became a fact.

As a consultant, I have frequently been given platforms to write code for that I would prefer to exist on (what I consider to be) a better platform.

Well, you'll have to make up your mind: are you actually a consultant, or just a temporary extension of an existing team working a project? IMHO way too much technical "consulting" is actually the latter.

By the actual meaning of the word, a consultant is a person who gives advice. Sometimes that advice will have to be "The only way out of this mess is to start from scratch". Situations like that should be rare, but they exist.

The OP doesn't convey the impression that he fully knows what he's doing, nor that he's fully aware what consequence that will have. At that point, advice to the tone of "You're heading in the wrong direction", like Erik's, is perfectly justified.

 RE: Why bother with Banking?

why?

Because we live in the real world.

Even SiLabs - that bastion of high-end 8051 - now has ARM Cottex-M3 chips available...

I am sure someone will make Cottex-M3 chips sometime in the future but I doubt such a chip is available from anyone now, particularly Silabs.

 RE: Cottex-M3

Maybe a competitor for the Petnium?

 RE: Cottex-M3

Maybe a competitor for the Petnium?

That sounds more likely, :)

But this is a discussion forum - not the Real World...

More precisely, this is a discussion forum for real people talking about issues in the real world.

If you wish to talk about fantasy, I am sure there are other places for that where Keil products are not involved (I hope).

 RE: we live in the real world.

But this is a discussion forum - not the Real World...

 Woo Hoo - We're in the matrix

But this is a discussion forum - not the Real World...

And would you like to say how much time do you spend on forums?

Nah, probably best if you don't.

 RE: Address space overflow

Wooohoo hooooo.......guys wait. Please Relax and chill.
Dear Andrew and Reluctant Consultant, I think we got diverted from the main topic.

To Andrew and Reluctant Consultant, I have knowledge on Cortex-M3 and Cortex-M3 is used for all the new project development. This is a back dated project, on which a lot of development has been done. And changing the platform now would consume a lot of time as well as cost. Hence, my project manager will be negative on changing of platform.
Never the less, I would also, as my personal opinion, always work with latest controllers and technology. But, that's not in my hand. I'll have to get a break through on the existing problem.

Coming back to our issue....
Dear Dejan Durdenic, I have already read that datasheet (don't mean to sound rude or arrogant). Hence will you kindly highlight the exact paragraph, that gives the solution to my problem. I have read a lot of material on net, blogs and PDF's (For past 2 days, I am doing that).

Below are the details:

******** File1.lst file extracts ***********
******** Common Bank ***********
MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 21521 ---- CONSTANT SIZE = 2318 ---- XDATA SIZE = 165 38 PDATA SIZE = ---- ---- DATA SIZE = ---- ----
C51 COMPILER V8.06 COMMON 04/28/2012 12:10:22 PAGE 72

IDATA SIZE = ---- ---- BIT SIZE = 5 ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)

******** File2.lst file extracts ***********
******** Bank 1 ***********
MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 32745 ---- CONSTANT SIZE = 1850 ---- XDATA SIZE = 2469 34 PDATA SIZE = ---- ---- DATA SIZE = ---- ---- IDATA SIZE = ---- ---- BIT SIZE = 122 ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)

******** File3.lst file extracts ***********
******** Bank 2 ***********
MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 34208 ---- **refer the NOTE1 below. CONSTANT SIZE = 3569 ---- XDATA SIZE = 34 7 PDATA SIZE = ---- ---- DATA SIZE = ---- ---- IDATA SIZE = ---- ---- BIT SIZE = 1 ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)

******** File3.lst file extracts *********
******** Bank 3 **********
MODULE INFORMATION: STATIC OVERLAYABLE CODE SIZE = 2316 ---- CONSTANT SIZE = 5952 ---- XDATA SIZE = 164 ---- PDATA SIZE = ---- ---- DATA SIZE = ---- ---- IDATA SIZE = ---- ---- BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)

NOTE1: I know that the file size (in BANK2) is greater than 32KB, but than the linker should not show address space overflow in 'BANK1'.
*** ERROR L107: ADDRESS SPACE OVERFLOW SPACE: BANK1

*** ERROR L107: ADDRESS SPACE OVERFLOW SPACE: BANK2

Below are the extracts of M51 file: TYPE BASE LENGTH RELOCATION SEGMENT NAME
* * * * * * * C O D E B A N K 1 * * * * * * * 0000H 9881H *** GAP *** NOTE2 BANK1 9881H 1D5BH UNIT BANK1 B5DCH 1756H UNIT BANK1 CD32H 0D51H UNIT BANK1 DA83H 0623H UNIT BANK1 E0A6H 05DDH UNIT BANK1 E683H 0541H UNIT BANK1 EBC4H 044EH UNIT BANK1 F012H 03D7H UNIT BANK1 F3E9H 03BCH UNIT BANK1 F7A5H 033AH UNIT BANK1 FADFH 0322H UNIT BANK1 FE01H 01B4H UNIT BANK1 FFB5H 004BH UNIT

* * * * * * * C O D E B A N K 2 * * * * * * * 0000H 9881H *** GAP *** NOTE2 BANK2 9881H 03CCH UNIT BANK2 9C4DH 02A7H UNIT BANK2 9EF4H 02A7H UNIT BANK2 A19BH 0205H UNIT BANK2 A3A0H 0175H UNIT
BL51 BANKED LINKER/LOCATER V6.05 04/30/2012 09:54:32 PAGE 5

BANK2 A515H 00F6H UNIT BANK2 A60BH 00B2H UNIT BANK2 A6BDH 0079H UNIT BANK2 A736H 0053H UNIT

* * * * * * * C O D E B A N K 3 * * * * * * * 0000H 9881H *** GAP *** NOTE2 BANK3 9881H 06ECH UNIT BANK3 9F6DH 0220H UNIT

NOTE2: Why does Bank start from 9981H and not from 8000H as stated in the datasheets?
Prior to latest compilation, the starting address was A185H. And during that compilation,

the size of code overflowing + starting address = bank size

I fail to understand, why the starting address is not '8000H' as it should be?
Kindly assist.

Dhaval

 RE: better view of files

******** File1.lst file extracts ***********
******** Common Bank ***********
MODULE INFORMATION:   STATIC OVERLAYABLE
   CODE SIZE        =  21521    ----
   CONSTANT SIZE    =   2318    ----
   XDATA SIZE       =    165      38
   PDATA SIZE       =   ----    ----
   DATA SIZE        =   ----    ----
C51 COMPILER V8.06   COMMON                                                                04/28/2012 12:10:22 PAGE 72
   IDATA SIZE       =   ----    ----
   BIT SIZE         =      5    ----
END OF MODULE INFORMATION.

******** File2.lst file extracts ***********
******** Bank 1 ***********
MODULE INFORMATION:   STATIC OVERLAYABLE
   CODE SIZE        =  32745    ----
   CONSTANT SIZE    =   1850    ----
   XDATA SIZE       =   2469      34
   PDATA SIZE       =   ----    ----
   DATA SIZE        =   ----    ----
   IDATA SIZE       =   ----    ----
   BIT SIZE         =    122    ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)

******** File3.lst file extracts ***********
******** Bank 2 ***********
MODULE INFORMATION:   STATIC OVERLAYABLE
   CODE SIZE        =  34208    ----
   CONSTANT SIZE    =   3569    ----
   XDATA SIZE       =     34       7
   PDATA SIZE       =   ----    ----
   DATA SIZE        =   ----    ----
   IDATA SIZE       =   ----    ----
   BIT SIZE         =      1    ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)

******** File3.lst file extracts *********
******** Bank 3 **********
MODULE INFORMATION:   STATIC OVERLAYABLE
   CODE SIZE        =   2316    ----
   CONSTANT SIZE    =   5952    ----
   XDATA SIZE       =    164    ----
   PDATA SIZE       =   ----    ----
   DATA SIZE        =   ----    ----
   IDATA SIZE       =   ----    ----
   BIT SIZE         =   ----    ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)

NOTE1: I know that the file size (in BANK2) is greater than 32KB, but than the linker should not show address space overflow in 'BANK1'.
*** ERROR L107:
    ADDRESS SPACE OVERFLOW SPACE: BANK1

*** ERROR L107:
    ADDRESS SPACE OVERFLOW SPACE: BANK2

Below are the extracts of M51 file:
            TYPE    BASE      LENGTH    RELOCATION   SEGMENT NAME
 * * * * * * *   C O D E   B A N K   1   * * * * * * *
                    0000H     9881H                  *** GAP ***       NOTE2
            BANK1   9881H     1D5BH     UNIT
            BANK1   B5DCH     1756H     UNIT
            BANK1   CD32H     0D51H     UNIT
            BANK1   DA83H     0623H     UNIT
            BANK1   E0A6H     05DDH     UNIT
            BANK1   E683H     0541H     UNIT
            BANK1   EBC4H     044EH     UNIT
            BANK1   F012H     03D7H     UNIT
            BANK1   F3E9H     03BCH     UNIT
            BANK1   F7A5H     033AH     UNIT
            BANK1   FADFH     0322H     UNIT
            BANK1   FE01H     01B4H     UNIT
            BANK1   FFB5H     004BH     UNIT

            * * * * * * *   C O D E   B A N K   2   * * * * * * *
                    0000H     9881H                  *** GAP ***        NOTE2
            BANK2   9881H     03CCH     UNIT
            BANK2   9C4DH     02A7H     UNIT
            BANK2   9EF4H     02A7H     UNIT
            BANK2   A19BH     0205H     UNIT
            BANK2   A3A0H     0175H     UNIT
BL51 BANKED LINKER/LOCATER V6.05            04/30/2012  09:54:32  PAGE 5

            BANK2   A515H     00F6H     UNIT
            BANK2   A60BH     00B2H     UNIT
            BANK2   A6BDH     0079H     UNIT
            BANK2   A736H     0053H     UNIT

            * * * * * * *   C O D E   B A N K   3   * * * * * * *
                    0000H     9881H                  *** GAP ***
            BANK3   9881H     06ECH     UNIT
            BANK3   9F6DH     0220H     UNIT

NOTE2: Why does Bank start from 9981H and not from 8000H as stated in the datasheets?
Prior to latest compilation, the starting address was A185H. And during that compilation,

the size of code overflowing + starting address = bank size

 RE: better view of files

You talk about information 'as stated in the datasheets'. I don't follow that part. The linker does not know (or read) the datasheets so it has to rely on what is provided to it.

Though quite interesting, the result of the linkage is probably not the best information to provide.

What I think would be more useful is the detail relating to the information provided to the linker.

Depending upon your listing settings, this information can be given at the start of the map file.

What you need to look at are the specifications relating to the common and the banked areas.

 RE: better view of files

To Reluctant Consultant.
1. What I think would be more useful is the detail relating to the information provided to the linker.
Are you referring to the following information:

Tool Chain Integration (window in SiLabs)
Tool Vendor: Keil

Assembler Tab:
   Command Line Flags:
      XR GEN DB EP NOMOD51.

Compiler Tab:
   Command Line Flags:
      DB OE BR OR OT(8,Size) Large.

Linker Tab:
   Command Line Flags:
      RS(256) PL(68) PW(78) BANKAREA(8000H,0FFFFH).

2. What you need to look at are the specifications relating to the common and the banked areas.
Kindly elaborate, what I need to look at. I mean to say, I didn't exactly understand this line.

The datasheet specifications:

Common Bank Area:  0000H to 8000H
Bank1 Area:        8000H to FFFFH
Bank2 Area:        8000H to FFFFH
Bank3 Area:        8000H to F7FFH

1KB of Address reserved in Bank3 (F800H to FFFFH).

 RE: better view of files

The tool chain information is better, but I think that the information in the map file would be the most certain way of looking at the settings.

For example, in an old project of mine, the map file produced by the linker has a block of text that starts:

BL51 BANKED LINKER/LOCATER V5.03, INVOKED BY:
C:\KEIL\C51\BIN\BL51.EXE BANK1 {.....etc.......}

The link settings used at time of the linker invokation should show what details are being specified for the common and banking details.

We can see from your details:

BANKAREA(8000H,0FFFFH)

So, the simplistic view would be that your banked code should start at 0x8000, but you need to check other parameters that might cause it to be starting further up.

 RE:Commnad Line Options

The following extract from M51:

BL51 BANKED LINKER/LOCATER V6.05, INVOKED BY:
C:\KEIL\C51\BIN\BL51.EXE
D:\dhaval's disso\DissoVer4.41C_i2c\common.obj, D:\dhaval's disso\DissoVer4.41C_i2c\L51_BANK.obj, BANK1
{D:\dhaval's disso\DissoVer4.41C_i2c\main.obj}, BANK3
{D:\dhaval's disso\DissoVer4.41C_i2c\screens.obj}, D:\dhaval's disso\DissoVer4.41C_i2c\STARTUP.obj, BANK2
{D:\dhaval's disso\DissoVer4.41C_i2c\menu.obj} TO D:\dhaval's disso\DissoVer4.41C_i2c\TDT08L

RS (256) PL (68) PW (78) BANKAREA (8000H, 0FFFFH)

So, the simplistic view would be that your banked code should start at 0x8000, but you need to check other parameters that might cause it to be starting further up.

What type of Parameters are you referring to? Can you give an example?

 RE:Commnad Line Options

What type of Parameters are you referring to? Can you give an example?

No. That's why you need to look at the settings carefully. There's obviously something missing or incorrect, otherwise it would be producing the output you expect.

 RE: Commnad Line Options

Keil Compiler Options:
Under Listing:
Marked Check boxes:
 1. Generate .lst file
 2. Include Conditional code

Warnings: Level 2

Optimization Level:
Level 10 [Rearrange Code (Linker Optimization)]
Emphasis Favor Small Code

Memory Model:
Variable Location:
Large: XDATA
Code Size Limits: 64K Functions


Keil Linker Options:
Under Linking:
Marked Check boxes:
 1. Enable Variable Overlaying

RAM Size: 256
Selected Processor: C8051F120

 RE: Commnad Line Options

Set the option to produce a linker map file, enable everything, do a rebuild (if necessary) and look for the information at the start that begins with something like:

BL51 BANKED LINKER/LOCATER V5.03, INVOKED BY:
C:\KEIL\C51\BIN\BL51.EXE BANK1 {.....etc.......}

 Possible reason

I think you need to examine details relating to the 'common area'. I suspect the common code might be being placed at the start of each bank.

You mention that the datasheet specifies:

Common Bank Area:  0000H to 8000H
Bank1 Area:        8000H to FFFFH
Bank2 Area:        8000H to FFFFH
Bank3 Area:        8000H to F7FFH

But, there is no specification of the common area in the linker invocation.

For example, my old project (which seems to have similarities to your memory layout) has a linker invocation containing:

BANKAREA (0X8000, 0XFFEF) RAMSIZE (256) DISABLEWARNING (16) CODE (0X0000-0X7FFF) XDATA (0X0000-0XFFFF)

Note the 'code' which I did not see in your linker invocation.

 RE: My observation

My observations, conclusions and Solution to Address Space Overflow

* * * * * * *   C O D E   M E M O R Y   * * * * * * *
CODE    0000H     0003H     ABSOLUTE
CODE    0003H     0007H     UNIT
        000AH     0001H                  *** GAP ***
  .       .         .        .
  .       .         .        .
  .       .         .        .
  .       .         .        .
CODE    97F5H     001FH     UNIT
CODE    9814H     001EH     UNIT
CODE    9832H     0012H     UNIT
CODE    9844H     0010H     UNIT
CODE    9854H     000BH     UNIT
CODE    985FH     000AH     UNIT
CODE    9869H     000AH     UNIT
CODE    9873H     0007H     UNIT
CODE    987AH     0007H     UNIT      end address = starting address of function + length Refer NOTE
                                      end address = 987A + 7 = 9981 
* * * * * * *   C O D E   B A N K   1   * * * * * * *
        0000H     9881H                  *** GAP ***    Refer NOTE
BANK1   9881H     1D5BH     UNIT
BANK1   B5DCH     1756H     UNIT
BANK1   CD32H     0D51H     UNIT
BANK1   DA83H     0623H     UNIT
BANK1   E0A6H     05DDH     UNIT
BANK1   E683H     0541H     UNIT
BANK1   EBC4H     044EH     UNIT
BANK1   F012H     03D7H     UNIT
BANK1   F3E9H     03BCH     UNIT
BANK1   F7A5H     033AH     UNIT
BANK1   FADFH     0322H     UNIT
BANK1   FE01H     01B4H     UNIT
BANK1   FFB5H     004BH     UNIT

* * * * * * *   C O D E   B A N K   2   * * * * * * *
        0000H     9881H                  *** GAP ***     Refer NOTE
BANK2   9881H     03CCH     UNIT
BANK2   9C4DH     02A7H     UNIT
BANK2   9EF4H     02A7H     UNIT
BANK2   A19BH     0205H     UNIT
BANK2   A3A0H     0175H     UNIT
BANK2   A515H     00F6H     UNIT
BANK2   A60BH     00B2H     UNIT
BANK2   A6BDH     0079H     UNIT
BANK2   A736H     0053H     UNIT

* * * * * * *   C O D E   B A N K   3   * * * * * * *
        0000H     9881H                  *** GAP ***      Refer NOTE
BANK3   9881H     06ECH     UNIT
BANK3   9F6DH     0220H     UNIT

The following is my conclusion.

NOTE: The starting address of each bank = End address of common bank + 1

When I shifted some piece of the code from common bank into other banks, I found that the starting address of each bank in the M51 file (A part of which i have shown above), changed.

However, a very good solution is change the Code Optimization level to Level10. Go to:

Project -> Tool Chain Integration -> Compiler (Tab) -> Customize -> Optimization -> Level

Select "Level 10: Rearrange Code (Linker Optimization)".
Save Project and click on "Rebuild" or press "Ctrl + Shift + F7" keys.

Now write your code in any bank without worrying about linking. The linker will take care of everything. It rearranges the code in each bank and hence will generate the hex file with minimum code size.

 RE: My observation

OOps! Made a mistake in addition in my previous post.

987A + 7 = 9881

Sorry.

 Code Banking Problem Solved

Dear All,
If in case you find my observations wrong, or have any other solution, kindly inform me.

Thank you for all the necessary help, guidance and valuable time you provided. Learnt a lot.
Hope the observations and conclusions helps other newbies to solve the problems related to 'Code Banking' and 'Address Space Overflow'.

Regards,
Dhaval Solanki

 Not bad for 'a bodge'

Glad to see you've got it going.

Regardless of what anyone else might say about banking, I think what Keil did to provide the mechanism is really pretty smart. Certainly for the application I used it on, the results were perfectly acceptable; in terms of development time, reliablility and end product costs. And, after the initial learning curve in getting it going, the fact that we were using banking was virtually forgotten about.

That said, for any new projects, I would recommend you keep an open mind and consider something different.

 RE: Not bad for 'a bodge'

Dear,
I already highlighted
... Cortex-M3 is used for all the new project development. ... Never the less, I would also, as my personal opinion, always work with latest controllers and technology. .

I am glad that Keil has provided the feature "Optimization: Level 10: Rearrange Code (Linker Optimization) ". I mean they should, to be the best IDE software developers. Respect.

But i still Fail to understand

The starting address of each bank = End address of common bank + 1

This should not happen, ideally.

 RE: Not bad for 'a bodge'

But i still Fail to understand

The starting address of each bank = End address of common bank + 1

This should not happen, ideally.

On the contrary: that must happen. Your believing otherwise indicates you don't really understand how banking works.

The common bank is called a "common bank" because it contains the material that has to be commonly accessible to code in all banks. The only way that can work is if the entire address range of the common bank is reserved and kept available, regardless which other banks are mapped. In a scheme like SiLabs', with a 32KiB+32KiB hardwired bank mapping, the only way the common bank can become bigger than 32 KiB is if all bytes beyond the 32 KiB boundary are copied to all 3 "upper" banks, so they'll be accessible regardless which of the upper banks is currently active.

I think your real problem was that in your original configuration you placed too much stuff into the common bank yourself, causing this spill-over mechanism to be triggered.

 RE: Not bad for 'a bodge'

Dear Hans-Bernhard Broeker,
Thank you for clearing the air. But, in my opinion, there should be a document produced by the chip vendor stating this. A newbie may not understand this, the very first time he is using the IC, or may not have a clear picture unless he faces a problem like me.

Dhaval

 RE: Not bad for 'a bodge'

But, in my opinion, there should be a document produced by the chip vendor stating this.

Though it might be helpful if the chip vendor produced application notes or other documentation relating to such things, I don't think it is really something that they should be expected to do. Which compiler vendors would they document for? Where would they stop?

The Keil documentation relating to banking is reasonably good and:

http://www.keil.com/support/man/docs/bl51/bl51_codebanking.htm

It just requires the reader to have an appreciation of what it is trying to achieve and what is possible.

 RE: Not bad for 'a bodge'

But, in my opinion, there should be a document produced by the chip vendor stating this.
well, SILabs does

The Keil documentation relating to banking is reasonably good and:
but is somewhat invalid for the SILabs (and other?) chips with "internal banking"

go by the SILabs appnote, it is crystal clear

Erik

 RE: Not bad for 'a bodge'

go by the SILabs appnote, it is crystal clear

I'll take your word for it :)

 RE: Commnad Line Options

Just a hint - C51 linker does not show composite CODE+CONSTANT size. So, your BANK1 module
takes 32745 bytes of CODE + 1850 bytes of CONSTANT space which together gives more than 32768 bytes. Try to solve BANK1 and BANK2 sizes first...

- Dejan

 RE: Address space overflow

This is a back dated project, on which a lot of development has been done. And changing the platform now would consume a lot of time as well as cost.

The problem with that argument is that changing from an ordinary '51 to a 128 KiB banked configuration is to quite some extent just the thing you say you want to avoid: a change of platform.