SDRAM issue

Hi All,

We have interfaced 1 SDRAM to LPC3250 (Lower 16 bit data line) .This SDRAM is from Micron technolgies 32 MB(MT48LC16M16A2).

Now problem is that we are not sure whether ,can we run our application code from the SDRAM ,because access from processor will be 32 bit wide , since we didn't connected anything on upper data line we will read junk values .

After seeing the refrence schematics provided by NXP we concluded that there is mistake in our hardware we should have connected 2 SDRAM (one on upper 16 bit and othe on Lower 16 bit) .

Question :

Is there still some way to run our code , can we build our code with THUMB instruction (16 bit)and run the code.

Please give your valuable feedback.

Thanks & Regards
Sumit

 RE: SDRAM issue

If the memory controller have a 16-bit/32-bit configuration setting, then it will fail.

Thumb means 16-bit base size of instructions - but they are still stored directly after each other. No room for 16 bit data, 16-bit junk, 16-bit data, 16 bit junk...

 RE: SDRAM issue

memory controller support both 16 and 32 bit wide SDRAM support .

But why it fails if it support both ,can you please elaborate it.

 RE: SDRAM issue

If it has support for just 16-bit data width, then it must also have a configuration setting informing it that you only use 16-bit data width. Have you found such a configuration, and made sure it is correct?

 RE: SDRAM issue

Hi all,

We configured LPC3250 to 16 bit mode but still we are not able to write into locations which are multiple of 2 as seen in log.
Write operation is short (16 bit) ,below are the logs of write and read to SDR-SDRAM.

Only one SDR-SDRAM is interfaced to LPC3250 on

Chip select - EMC_DYCS0
Data Bus D0- D15
Address Line A0- A14
EMC_DQM0
EMC_DQM1
EMC_CLK
EMC_CLKEN
EMC_RAS
EMC_WR
EMC_CAS
EMC_CLK

Write :
Mem Loc: value
0x80000000 0x1111
0x80000002 0x2222
0x80000004 0x3333
0x80000006 0x4444
0x80000008 0x5555
0x8000000A 0x6666

Read :
Mem Loc: value
0x80000000 0x1111
0x80000002 0x1111
0x80000004 0x3333
0x80000006 0x3333
0x80000008 0x5555
0x8000000A 0x5555

Please throw some light on the matter

Thanks & Regards
Sumit

 RE: SDRAM issue

Hi all,

To the earlier post we would like to add another observation

if write happens only on location which are offset of 2 starting from 0x80000002, when we are reading nothing is written into memory please refer below log for clarity

Write :
Mem Loc: value

0x80000002 0x2222
0x80000006 0x4444
0x8000000A 0x6666

Read :
Mem Loc: value
0x80000000 0x33cc
0x80000002 0x33cc
0x80000004 0x33cc
0x80000006 0x33cc
0x80000008 0x33cc
0x8000000A 0x33cc

Please throw some light on the matter

Thanks & Regards
Sumit

 RE: SDRAM issue

"But why it fails if it support both ,can you please elaborate it"

"Please throw some light on the matter"

You must configure both the controller and the SDRAM correctly. There are plenty of combinations that don't work correctly - Looks like you've got one of them.

 RE: SDRAM issue

But if it is configuration problem then we should not write a single location properly,Can you provide any link where we can find some code (tested) where LPC3250 is interfaced with SDRAM on 16 bit interface for cross checking our code.

Thanks & Regards
Sumit

 RE: SDRAM issue

"But if it is configuration problem then we should not write a single location properly"

That is not correct. There are many configuration combinations - Some of those can appear to partially work.

 RE: SDRAM issue

If the processor thinks the memory interface is 32 bit wide but the interface is only 16 bit wide, you obviously have a good change that a 4 byte wide write at first address of the memory will result in two of the bytes being correctly saved (since they map to the existing 16 bits) and two bytes fails to save. If you only test using 16-bit integers, you will not notice this.

Don't be so quick making assumptions. Only assume what you can prove. What you can't prove should be downgraded to maybe a suspicion. After all, a large percentage of all software errors are caused by people who have made incorrect assumptions.

 RE: SDRAM issue

Did you look at MDK example found in \ARM\Boards\Phytec\LPC3250\Blinky\ for reference?

 RE: SDRAM issue

hi,
we have gone through blinky example,that interface is for 32 bit wide ,our case is only one SDRAM connected to DSY_CSO with 16 bit data bus

Thanks & Regards
Sumit

 RE: SDRAM issue

You need to configure the memory controller for 16 bit sdram, then 32 bit access will be treated as a pair of 16 bit accesses.

this means that you need to set the SDRAM controller for 16 bit memory, it will use 4 words buffers for memory accesses, but these will be translated into 8 word accesses to the SDRAM since the SDRAM controller buffers 4 32 bit words and the SDRAM needs to provide 8 16 bit words.
You need to take care when programming the SDRAM devices to ensure that the CAS and Burst length settings are correctly aligned when writing the mode register.
Since the memory is actually 16 bits you reduce the address shift by 1 bit compared to using 32 bit sdram, also take care that it is correctly aligned depending on the SDRAM controller mode ( Row,Bank,Column, or Bank,Row,Column).

so generally you will use a shift of ColumnAddressBits + 1 for Bank,Row,Column, and ColumAddressBits + 3 for RowBankColumn (assuming that there are 4 banks).

there is a good app note on the LPC forum ( LPCWARE.com ).
regards

Phil.

 RE: SDRAM issue

Thanks for reply

from your reply we draw following Conclusion

1) Configure SDRAM Controller in 16 bit mode

2) Do 32 bit Access ?

but can we do 32 bit access when actually we are configuring SDRAM Controller for 16 bit and secondly what about 16 upper bit ,they are not physically mapped on hardware ,will processor do the buffering as you told because processor data sheet do not mention anything about it.

Can we get any reference code where LPC3250 is interfaced to single SDRAM via 16 bit SDRAM.

 RE: SDRAM issue

As have been mentioned long time a go - yes, if it is supported to configure the memory controller for use with a 16-bit memory you obviously have to do that. If it isn't supported, you are busted.

Next thing - if the memory controller supports 16-bit wide memory, then it will allow the processor core to perform 32-bit accesses. These 32-bit accesses will be converted into two 16-bit accesses to they memory. All the difference it makes to the processor core is that the memory accesses will be slower because the two 16-bit accesses must be made after each other.

 RE: SDRAM issue

"... because processor data sheet do not mention anything about it."

What processor information are you looking at?

In UM10326, section 7.2 (Features of the EMC) it states:

• 16-bit and 32-bit wide SDRAM memory support

That same chapter also has a note that says:

For SDRAM chip selects that are configured for 32-bit wide transfers, single SDRAM bursts are used. When SDRAM chip selects are configured for 16-bit wide transfers, a burst length of 2 is used. Mode registers in related SDRAM devices must be programmed accordingly.

Table 115 has a good table too.

Plenty for you to check out.