Hello, I have an 8051 custom processor, this have a memory mapped like this: 16 banks of eeprom external memory of 32kB each one. The page 0 is mapped: 0x0000-0x7FFF. The other ones: 0x8000-0xFFFF. The page number is selected via a PAGE_REG. Also I have a block of extended ram which is mapped from 0x1000-0x1FFF. And I have two RAMs more: internal ram (indirect and direct address), and external ram, of 256B amount (from 0x00 to 0xFF). Memory access from C, I do this: For eeprom:
//... select mem_page ... unsigned char pdata *ptr; ptr = address; *ptr = dat;
For extended ram:
unsigned char xdata *ptr; ptr = address // 0x1000 <= address <= 0x1FFF *ptr= dat;
For internal ram:
unsigned char idata *ptr; ptr = address; *ptr = dat;
The extended ram, and internal ram works, but the eeprom access doesn't. Someone can guide me? Thanks a lot.
g.
16 banks of eeprom external memory of 32kB each one is it not about time you switch to an ARM?
Erik
My dear friend: when its depends on me, so will do... PS: my english is not the better, so plis, have compassion.. =)
The extended ram, and internal ram works, but the eeprom access doesn't. the EEPROM (unless there is a language thing here) is serial. To use serial code memory there is, somewhere, (I would'nt touch it, the speed will be miserable) a 'very special' version of paging which will be required.
"the EEPROM (unless there is a language thing here) is serial"
EEPROM need not be serial. EEPROM is basically the same thing as flash memory - it's just a question of how fast you can erase the memory.
EEPROM need not be serial. EEPROM is basically the same thing as flash memory - it's just a question of how fast you can erase the memory. this is exactly why I asked. most people call serial flash devices EEPROM and parallel EEPROMs Flash
For eeprom:
You're not making any sense there. pdata is not eeprom memory --- it's not even close. Nor will any EEPROM just let itself be written to just by executing an PDATA write access.
Thanks for your answer. The EEPROM memory is mapped like I told before. The page0 (0-0x7FFF) contains the code of the software that executes the processor. The other pages (mapped 0x8000-0xFFFF) contains data that can be written and read from the memory. The access to the memory is by doing the code I post before. I tried to do by treating memory like xdata, and it works, but I don´t have other method to verificate that the correct memory write is the EEPROM... Thanks a lot.
PS: Again sorry by my english. =)
I'm not sure that's true any more - it is quite common nowadays to refer to Flash as EEPROM.
After all, "EEPROM" just stands for Electrically-Eraseable PROM - which is a perfectly valid description of Flash (as distinct from UV-EPROM).
Yes. The name flash just means an EEPROM that has been improved to allow quick-erase of large sections of the memory in constant time, while a normal EEPROM either erases cell-for-cell or have a large number of very small sectors that are erased one-by-one.
Some microprocessors have EEPROM that allows direct writes as if RAM. For external chips, you often have situations where you can perform direct writs as if RAM, but an additional interface to check if chip is ready for more writes. Sometimes, the writes are just cached in a small RAM buffer hidden within the EEPROM, and a special command is used to force the write of this sector.
I have an 8051 custom processor not very informative
anyhow with that (lack of) knowledge is !RD and !PSEN NEGATIVE ORed (some idiots will say anded) to the EEPROMs !RD
The 8052 has several non overlaping memory areas. As far a paging you have code and XData. the question is what did bank and how is it banked. Did you read the banking instructions in the manual? you need you supply the paging functions for the compiler to use.
Thanks for your answer. Now I'm able to tell you the solution adopted. I have addressing the ram as pdata, and the extram and e2rom as xdata,in this case, the processor is able to determine the memory mapped with the address provided.