Hello,
This is not a Keil specific question, but I was hoping that somebody would be able to clarify the following as I don't have a lot of experience with Cortex M0 chips (I have a LPC1114 at my disposal):
I understand that unlike Cortex M3s, a Cortex M0 always runs in privileged mode. Therefore,
__disable_irq() ;
always disables the interrupts.
What is then the purpose of the SVC instruction on a Cortex M0? It is supposed to switch the core to a privileged mode just like a ARM7's SWI instruction, but apparently it is not necessary...? If so, I also don't need to do anything special when jumping from a bootloader to the application (in terms of processor mode), right?
I guess one use of SVC is to trigger some functions, like OS stuff that is tied to the SVC handler. But from a functional point of view, it seems to be void on a Cortex M0.
Going back to the origins of ARM and the SWI, I always saw the point of it as being an entry point into an OS - And the disable of interrupts was a consequence rather than the reason.
Surely that argument still holds true. Many older processors had equivalents. Even the lowly Z80 had their RST instructions.
Have you got a copy of "The Definitive Guide to the ARM Cortex-M0"? That might give some extra insight.
I do have a copy, and it states that the processor runs in privileged mode - always. Chapter 18 (Using SVC) states that "the SVC is rarely used directly without the OS". I guess that answers my question. I read a lot lately and somehow I mixed up the requirement to disable interrupts from privileged mode of a Cortex M3 and a Cortex M0, where it is always allowed (I even created a tiny project to disable the systick interrupt). Thanks for your reply.
> What is then the purpose of the SVC instruction on a Cortex M0?
I believe it allows an OS to switch between contexts _without_ actually disabling interrupts. ARM describes this method of context switching in their architecture technical reference manuals.
The advantage of this method is that interrupt latencies aren't adversely affected, as they would be if context switches were done by using a critical area with disabled interrupts. Look for a chapter titles "Use of SVCall and PendSV to avoid critical code regions".
Same thing goes for the LDREX/STREX/CLREX instructions - their functionality can easily be achieved by using a critical region with disabled interrupts, however, by using these instructions, interrupt latencies will be lower.
I believe that another strong argument for SVC is forward compatibility. Essential parts of an RTOS work on all Cortex-M processors whether they make use (or even know) of different privileges or not.
> LDREX/STREX/CLREX instructions - their functionality can easily be achieved by using > a critical region with disabled interrupts
Of course that'd work only in single master systems. The exclusive access primitives have been designed for systems with several bus masters. ARM11 was the first core that came with these instructions.
-- Marcus http://www.doulos.com/arm/