problem with PLL values choosing for LPC2939 (or LPC29xx) could anybody give me an example for following steps?? i want 125MHz in Fclkout
Values of the dividers are chosen with the following process: 1. Specify the input clock frequency Fclkin 2. Calculate M to obtain the desired output frequency Fclkout with M = Fclkout / Fclkin 3. Find a value for P so that Fcco = 2×P / Fclkout 4. Verify that all frequencies and divider values conform to the limits