I am modifing the ILVL of PSW within an ISR (level 15) to reduce the CPU priority (level 10) in order to allow other ISRs to interrupt the current function after the most time-critical part is over.
The ISR is using a separate RegisterBank (declared with the "using" attribute). It seems that due to the seperate RegisterBank no other ISR is able to interrupt the function after PSW is modified accordingly.
I did not expect this behaviour (not an expert). Is it correct or do I have to take care for additional things to make this mechanism work?
It seems that due to the seperate RegisterBank no other ISR is able to interrupt the function after PSW is modified accordingly.
This sounds unlikely. Why do you think register banks are to blame?
This sounds like an odd thing to do. This could probably cause problems, although I can't think of the exact nature of those problems right now. It's been years since I programmed a C167.
A more natural thing to do would be to split your ISR into two: one assigned to a high-priority interrupt (level 15), and the other one assigned to a lower-priority one (level 10). Then you can trigger the lower-priority interrupt at the end of the higher-priority ISR.
This sounds like an odd thing to do.
You're right. Triggering the lower-priority interrupt at the end of the higher-priority ISR is the better solution and it is the one I am using now. All the problems I had seem to be gone now.
Thanks a lot for your support!