Dear Experts, I am a newbie to Keil and using the PK51 development kit with Rev:9.03 to develop firmware for my CC2430 controller. The problem I am seeing is, when ever I create a large array (ex: unsigned char a[20]) , I was unable to initialize the values in the array. I can see the array has been created in XDATA. However if I create unsigned char IDATA a[20], I was able to initialize the array.
One more observation is, after executing the code for a couple of seconds (not exactly), the execution was looping in the following lines of code (STARTUP.A51).
XDATALOOP: MOVX @DPTR,A INC DPTR DJNZ R7,XDATALOOP DJNZ R6,XDATALOOP
The XDATA initialization as per my startup code is XDATASTART EQU 0x0100
XDATALEN EQU 0x1000
Can anyone let me know whats happening in my code. Please let me know, if any additional information is required to analyze the situation.
Also, Please forward me any available CC2430 Keil project.
Thanks in advance, Regards, RD
XDATASTART EQU 0x0100 why not 0? MOVX @DPTR,A INC DPTR DJNZ R7,XDATALOOP DJNZ R6,XDATALOOP why post unreadable, why initailize 64k when you only have 8, the time sounds right
Thanks for the help. Here is the modified STARTUP.A51, with which the code hangs after executing a couple of functions. I am sorry for asking to analyze the whole file. -RD
$NOMOD51 STACKSIZE EQU 0x85 ; must not exceed IDATA SEG ;------------------------------------------------------------------------------ ; ; User-defined <h> Power-On Initialization of Memory ; ; With the following EQU statements the initialization of memory ; at processor reset can be defined: ; ; <o> IDATALEN: IDATA memory size <0x0-0x100> ; Note: The absolute start-address of IDATA memory is always 0 ; The IDATA space overlaps physically the DATA and BIT areas. IDATALEN EQU 0 ;080H ; ; <o> XDATASTART: XDATA memory start address <0x0100-0xFFFF> ; The absolute start address of XDATA memory ;XDATASTART EQU 0x0100 XDATASTART EQU 0x0 ; ; <o> XDATALEN: XDATA memory size <0xE000-0xFD55> ; The length of XDATA memory in bytes. ;XDATALEN EQU 0x1000 XDATALEN EQU 0x0 ; ; <o> PDATASTART: PDATA memory start address <0x0-0xFFFF> ; The absolute start address of PDATA memory PDATASTART EQU 0x00 ; ; <o> PDATALEN: PDATA memory size <0x0-0xFF> ; The length of PDATA memory in bytes. PDATALEN EQU 0H ; ;</h> ;------------------------------------------------------------------------------ ; ;<h> Reentrant Stack Initialization ; ; The following EQU statements define the stack pointer for reentrant ; functions and initialized it: ; ; <h> Stack Space for reentrant functions in the SMALL model. ; <q> IBPSTACK: Enable SMALL model reentrant stack ; Stack space for reentrant functions in the SMALL model. IBPSTACK EQU 0 ; set to 1 if small reentrant is used. ; <o> IBPSTACKTOP: End address of SMALL model stack <0x0-0xFF> ; Set the top of the stack to the highest location. IBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1 ; </h> ; ; <h> Stack Space for reentrant functions in the LARGE model. ; <q> XBPSTACK: Enable LARGE model reentrant stack ; Stack space for reentrant functions in the LARGE model. XBPSTACK EQU 1 ; set to 1 if large reentrant is used. ; <o> XBPSTACKTOP: End address of LARGE model stack <0x0-0xFFFF> ; Set the top of the stack to the highest location. XBPSTACKTOP EQU 0x1EFF +1 ; 0x1EFF +1 ; </h> ; ; <h> Stack Space for reentrant functions in the COMPACT model. ; <q> PBPSTACK: Enable COMPACT model reentrant stack ; Stack space for reentrant functions in the COMPACT model. PBPSTACK EQU 0 ; set to 1 if compact reentrant is used. ; ; <o> PBPSTACKTOP: End address of COMPACT model stack <0x0-0xFFFF> ; Set the top of the stack to the highest location. PBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1 ; </h> ;</h> ;------------------------------------------------------------------------------ ; ; Memory Page for Using the Compact Model with 64 KByte xdata RAM ; <e>Compact Model Page Definition ; ; Define the XDATA page used for PDATA variables. ; PPAGE must conform with the PPAGE set in the linker invocation. ; ; Enable pdata memory page initalization PPAGEENABLE EQU 0 ; set to 1 if pdata object are used. ; ; <o> PPAGE number <0x0-0xFF> ; uppermost 256-byte address of the page used for PDATA variables. PPAGE EQU 0 ; ; <o> SFR address which supplies uppermost address byte <0x0-0xFF> ; most 8051 variants use P2 as uppermost address byte PPAGE_SFR DATA 0A0H ; ; </e> ;------------------------------------------------------------------------------ ; Standard SFR Symbols ; ACC DATA 0E0H B DATA 0F0H SP DATA 81H DPL0 DATA 82H DPH0 DATA 83H DPL1 DATA 84H DPH1 DATA 85H DPS DATA 92H NAME ?C_STARTUP ?C_C51STARTUP SEGMENT CODE ?STACK SEGMENT IDATA RSEG ?STACK DS STACKSIZE EXTRN CODE (?C_START) PUBLIC ?C_STARTUP CSEG AT 0 ?C_STARTUP: LJMP STARTUP1 RSEG ?C_C51STARTUP STARTUP1: IF IDATALEN <> 0 MOV R0,#IDATALEN - 1 CLR A IDATALOOP: MOV @R0,A DJNZ R0,IDATALOOP ENDIF IF XDATALEN <> 0 MOV DPTR,#XDATASTART MOV R7,#LOW (XDATALEN) IF (LOW (XDATALEN)) <> 0 MOV R6,#(HIGH (XDATALEN)) +1 ELSE MOV R6,#HIGH (XDATALEN) ENDIF CLR A XDATALOOP: MOVX @DPTR,A INC DPTR DJNZ R7,XDATALOOP DJNZ R6,XDATALOOP ENDIF IF PPAGEENABLE <> 0 MOV PPAGE_SFR,#PPAGE ENDIF IF PDATALEN <> 0 MOV R0,#LOW (PDATASTART) MOV R7,#LOW (PDATALEN) CLR A PDATALOOP: MOVX @R0,A INC R0 DJNZ R7,PDATALOOP ENDIF IF IBPSTACK <> 0 EXTRN DATA (?C_IBP) MOV ?C_IBP,#LOW IBPSTACKTOP ENDIF IF XBPSTACK <> 0 EXTRN DATA (?C_XBP) MOV ?C_XBP,#HIGH XBPSTACKTOP MOV ?C_XBP+1,#LOW XBPSTACKTOP ENDIF IF PBPSTACK <> 0 EXTRN DATA (?C_PBP) MOV ?C_PBP,#LOW PBPSTACKTOP ENDIF MOV SP,#?STACK-1 ; This code is required if you use L51_BANK.A51 with Banking Mode 4 ;<h> Code Banking ; <q> Select Bank 0 for L51_BANK.A51 Mode 4 #if 0 ; Initialize bank mechanism to code bank 0 when using L51_BANK.A51 with Banking Mode 4. EXTRN CODE (?B_SWITCH0) CALL ?B_SWITCH0 ; init bank mechanism to code bank 0 #endif ;</h> LJMP ?C_START END
Hi,
Is this problems solved? I encounter the same problem. When XDATALEN < 256 bytes it works fine. Larger values restart the code @ address 0x0000.
Thanks, Rob
Does your particular chip actually have > 256 bytes XRAM?
Have you correctly configured and/or enabled it? See the chip datasheet for specific details, SFRs, etc,...
Yes, the chip (Silabs C8051F920) has XRAM of 4096 bytes in the range of 0x0000 - 0x0FFF As far as i found out there is nothing special to do related to SFR to access the full 4K.
Have you used the on-chip debug to step through and see where, exactly, it fails?
In the meantime i have tested with single stepping and discovered that it goes wrong when the DPTR reaches 0x00EA. executing MOVX @DPTR,A with a DPTR of 0x00EA restarts the MCU.. I assume this is a question for Silicon Labs.
the ever repeated issue with SILabs deviates (f3x-up) is that the watchdog is enabled at reset. The startup code does not feed the dog, so it bites.
at the start of startup.a51 (prefererably a local copy) disable the watchdog and enable it asgain at th top of main.
Erik
My phobia for dogs has always play a big role in my life ;-)
Thanks !!