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XE167 question

Hi gentlemen
Consider i'm an absolute beginner with XE167 and microV4 too, so be patient with my stupid question.
I've enclosed a couple of uninterruptible instructions between _Atomic_(0) _endatomic_,
but wath happens to an hardware interrupt occuring at that time?
Is it neglected or simply delayed?
Thank's in advance
Alf

  • "Consider i'm an absolute beginner with XE167"

    So, rather than just give you an answer on a plate, here is the kind of approach that you could adopt to answer such questions for yourself:

    See the Keil C166 Manual for details of its _atomic_ and _endatomic_ routines.

    http://www.keil.com/support/man/docs/c166/c166__atomic_.htm

    It tells you that this causes an ATOMIC instruction to be insterted.

    The ATOMIC instruction is a part of the instruction set of the chip - it is not defined by Keil. Therefore, for details of what, exactly, the ATOMIC instruction does, you would have to refer to the manufacturer's documentation.

    You should also try searching the Keil site, putting "_atomic_" and "_endatomic_" into the 'Search' box:

    www.keil.com/.../search.asp

  • From the Manual...

    The atomic and extend instructions (ATOMIC, EXTR, EXTP, EXTS, EXTPR, EXTSR) disable the standard and PEC interrupts and class A traps until completion of the immediately following sequence of instructions.

    ATOMIC and EXTended instructions become active immediately, so no additional NOPs are required. All instructions requiring multi cycles or hold states for execution are considered to be one instruction. The ATOMIC and EXTended instructions can be used with any instruction type.

    Note: If a class B trap interrupt occurs during an ATOMIC or EXTended sequence, then the sequence is terminated, an interrupt lock is removed, and the standard condition is restored before the trap routine is executed. The remaining instructions of the terminated sequence executed after returning from the trap routine will run under standard conditions.

    Note: Certain precautions are required when using nested ATOMIC and EXTended instructions. There is only one counter to control the length of the sequence, i.e. issuing an ATOMIC or EXTended instruction within a sequence will reload the counter with the value of the new instruction.