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LPC 3250 Ethernet

Hi, I have designed LPC3250 based Ethernet communication board. Transmission is working whereas facing problem in data reception. Sometimes Data frames are getting detected in RX descriptors but data is getting corrupted. Always CRC and dribble nibble error bits are set in RX Status vector register (RSV). Presently HCLK (64MHz) is connected with MAC and also I have tried with different clock options. MDI CLK is 16MHZ connected to PHY. Circuit diagram is attached with this. Same configuration is working with LPC2468 processor. DP83848C PHY driver IC is used. MAC internal loop back test is working. Transmission is working. PHY loop back and BIST is failing. Reception is failing. The Same software code is working with LPC2468 Processor. Is there any difference or anything additionally taken care for LPC3250 Processor? What could be the reason? Please guide me