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A contraction between Keil and ST documentation

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Author
Tamir Michael
Posted
14-Apr-2008 07:14 GMT
Toolset
ARM
New! A contraction between Keil and ST documentation

Hello,
Maybe somebody from Keil can explain this; I still haven't tried it on the device itself, but it would be refreshing to understand the actual requirements.
Trying to run a STR9 at 96 MHz, I stubled upon the following guildelines:

KEIL (see http://www.keil.com/support/docs/3306.htm)
When you set the PLL post-divider value (PLL_PDIV) to 2 (hence: in order to run at 96 MHz), you must change the Clock Control Register (SCU_CLKCNTR) to the following:
* EMIRATIO: External Memory Interface Ratio fBCLK=HCLK/2
*

FMISEL: Flash Memory Interface Clock Divider FMICLK=RCLK/2

ST (see http://www.st.com/stonline/products/literature/an/13563.pdf)
The Flash memory interface clock (FMICLK) should have the same frequency as the RCLK clock (96 MHz)

this means no FMICLK dividers used

. As a result since Flash has a Sequential Burst read up to 96 MHz, we reduce execution time from there.

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Author
Robert Rostohar
Posted
14-Apr-2008 10:55 GMT
Toolset
ARM
New! RE: A contraction between Keil and ST documentation

STR91x Rev B had a problem with System reset at 96MHz (see http://www.st.com/stonline/products/literature/es/12280.pdf page 12). This was fixed in STR91X Rev D with date code 618 and later and in STR91xFA.

Basically on earlier silicon revisions it was not possible to use a 96MHz for FMI clock. This is not a problem anymore with new devices (especially for the STR91xFA to which the ST application note also refers to).

Based on this the Keil knowledgebase article describes the limitation for FMI clock to ensure that the Blinky example for MCBSTR9 board works with all silicon revisions of the STR91x chip. The article will be updated that this limitation applies only to the older silicon revisions.

Read-Only
Author
Tamir Michael
Posted
14-Apr-2008 11:37 GMT
Toolset
ARM
New! RE: A contraction between Keil and ST documentation

Robert,
Thanks a lot for your reply. I have read the errata sheet for the STR9 and I figured out what went wrong. But, I still have a question related to this issue: please see http://www.keil.com/support/docs/3215.htm. The statement "The JTAG on the STR9 device can be blocked by user code with invalid values for the register SCU_CLKCNTR (AHBDIV, RCLKDIV, MCLKSEL)" baffles me. Could you give an example for such values? I tried to run my device at 48 MHz with PCLK ticking at 12 MHz (and even 24 MHz) which resulted in the device becoming inaccessable and required the recovery procedure that is specified in the link. MCLKSEL was set to PLL, APBDIV to 1 (i.e. RCLK/2), RCLKDIV was 0 (=MSTRCLK) and FMISEL was 0. I had to set FMISEL to make this work. But why? What "invalid" settings does the link refer to (I didn't find these in the documentation)? Can the simulator warn of such settings?

Thanks in advance

Read-Only
Author
Robert Rostohar
Posted
14-Apr-2008 13:05 GMT
Toolset
ARM
New! RE: A contraction between Keil and ST documentation

I have experienced blocked JTAG in some user codes I've received and they all configured the clock improperly (invalid values in registers or clocks not in specified boundaries).

I haven't investigated into details and I don't remember the exact values anymore which caused the problems. I just know that such HW problem exist and provided a solution for JTAG recovery (maybe newer silicon revisions have less such problems).

Also I haven't seen this documented by ST however it happens on HW.

Read-Only
Author
Tamir Michael
Posted
14-Apr-2008 15:10 GMT
Toolset
ARM
New! RE: A contraction between Keil and ST documentation

Thanks a lot for your assistence.

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