Keil Logo

Peripheral Simulation

For Atmel AT91SAM7S161 — Advanced Interrupt Controller

Simulation support for this peripheral or feature is comprised of:

  • Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

Advanced Interrupt Controller Dialog

Advanced Interrupt Controller

The Advanced Interrupt Controller Dialog (available from the Peripherals menu) displays the status of all simulated ARM interrupts. The interrupt source, name, index, vector and type, and pending, mask and priority level status are displayed.

Selected Interrupt

To configure an interrupt, select the desired interrupt from the list and then use the controls in this section to change the vector address (AIC_SVR0), Type and Priority level for that interrupt. Use the Pending checkbox to trigger an interrupt, and the Mask checkbox to enable an interrupt.

  • AIC_IVR is the Interrupt Vector Register which contains the address of the current interrupt being processed.
  • AIC_FVR contains the address of the routine to be executed when a Fast Interrupt occurs.
  • AIC_ISR is the Interrupt Status Register which returns the source number(index) of the current interrupt .
  • AIC_IPR is the Interrupt Pending Register and displays the interrupts which are currently triggered, but not yet serviced.
  • AIC_IMR is the Interrupt Mask Register and displays the interrupts that are currently enabled (masked).
  • AIC_FFSR is the Fast Forcing Status Register that contains the status of internal and external interrupts.
  • AIC_CISR is the Core Interrupt Status Register that contains the state of the NFIQ and NIRQ signals.
  • AIC_SPU is the Spurious Vector Register which contains the address of the Spurious Interrupt handler. Use this text box to specify the vector address of your Spurious Interrupt routine.
  • AIC_DCR is the Debug Control Register used to enable and disable Protect Mode for debugging.
  • NFIQ is the state of the fast interrupt request input to the ARM processor. Only fast interrupts can enable this input. Internal and external interrupts cannot.
  • NIRQ is the state of the standard interrupt request input to the ARM processor. Internal (on-chip) and external interrupts can enable this input. Fast interrupts cannot.
  • PROT is the state of Protection Mode bit in Debug Control Register (AIC_DCR). If set, Protection Mode is enabled.
  • GMSK is the state of General Mask bit in Debug Control Register (AIC_DCR). If set, the NIRQ and NFIQ signals are held in the inactive state.

External Interrupt Pins

  • FIQ Fast Interrupt Request input pin.
  • IRQ0 External Interrupt Request 0 input pin.
  • IRQ1 External Interrupt Request 1 input pin.
Get more information about the
Peripheral Simulation Capabilities
of the µVision Debugger.
  Arm logo
Important information

This site uses cookies to store information on your computer. By continuing to use our site, you consent to our cookies.

Change Settings

Privacy Policy Update

Arm’s Privacy Policy has been updated. By continuing to use our site, you consent to Arm’s Privacy Policy. Please review our Privacy Policy to learn more about our collection, use and transfers
of your data.