Peripheral Simulation

For STMicroelectronics STR750FV1 — APB Bridge

Simulation support for this peripheral or feature is comprised of:

• Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

APB Bridge Dialog

The APB Bridge dialog configures the low-power, APB Bridge of the STR7x device. This bridge interfaces the serial peripherals such as I²C, UART, USB, etc.

Selected Peripheral

• Peripheral Clock Enable is checked to enable the peripheral clock for the selected peripheral.
• Peripheral Reset is checked to reset the selected peripheral.

Clock Disable & Software Reset

• MRCC_PCLKEN (Clock Enable Register) contains the peripheral clock disable bit settings.
• MRCC_PSWRES (Software Reset Register) controls the reset of the APB peripherals.