Peripheral Simulation

For Analog Devices ADuC7020 — UART

Simulation support for this peripheral or feature is comprised of:

• Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

UART Dialog

The Universal Asynchronous Receiver Transmitter (UART) Dialog configures UART. A UART transfers serial data to and from external devices and the ARM controller. The UART can be configured in a variety of ways to suit the external serial device.

Line Control Group

• COMCON0 (Communication Control Register) displays the combined control information for the following:
• WL (Word Length) selects the data character length of 5, 6, 7 or 8 bits per character.
• STOP (Number of Stop Bits) selects the number of stop bits to be sent with each character.
• Parity displays odd, even or no (forced "0" or "1") parity.
• EPS (Even Parity Select) is set for even parity and reset for odd parity.
• PEN (Parity Enable) is set to enable parity generation and checking.
• DLAB (Divisor Latch Access Bit) is set to calculate the baud rate based on the Divisor Latch register values.
• SP (Stick Parity) is set to force parity values based on the EPS and PEN settings.
• BRK (Break Control) is set to enable transmission of a Break.

Line Status Group

• COMSTA0 (Communication Status Register) displays the combined status information for the following:
• DR (Data Ready) set when the UART receives at least 1 character and the receiver hold register is not empty.
• THRE (Tx Holding Register Empty) is set when the transmission hold register is empty.
• TEMT (Transmitter Empty) set if there are no characters in the transmitter.
• OE (Overrun Error) set if the controller detects an overrun condition since the last status reset command.
• PE (Parity Error) set if the controller detects at least 1 false parity bit since the last status reset command.
• FE (Framing Error) set if the controller detects a framing error since the last status reset command.
• BI (Break Interrupt) is set when a Break condition occurs while receiving data.

Interrupt Enable Group

• COMIEN0 (Communication Interrupt Enable Register) displays the combined interrupt information for the following:
• ERBFI (Enable Receive Buffer Full Interrupt) is set to enable the interrupt when the buffer fills during a reception.
• ETBEI (Enable Transmit Buffer Empty Interrupt) is set to enable the interrupt when the transmit buffer empties.
• ELSI (Receive Status Interrupt Enable) is set to enable interrupt generation if DR, OE, PE or FE bits are set.
• EDSSI (Modem Status Interrupt Enable) is set to enable interrupt generation if DCTS, DDSR, TERI or DDCD bits are set.

Interrupt ID Group

• COMIID0 (Interrupt Identification Register) contains the Interrupt Identification status.
• ID displays the interrupt type(Line Status, Receive Buffer Full, Transmit Buffer Empty, Modem Status).

Divisor Latch & Baudrate Group

• COMDIV0 (Divisor Latch LSB Register) contains the lower 8-bit value that the MCU divides into the MCU clock (PCLK) to generate the UART baud rate.
• COMDIV1 (Divisor Latch MSB Register) contains the upper 8-bit value that the MCU divides into the MCU clock (PCLK) to generate the UART baud rate.
• COMDIV2 (16-bit Fractional Baud Rate Divide Register) contains the setting to allow a wider range and more accurate baud rates using the M and N values below.
• Baudrate is the computed UART baud rate.
• N the 11-bit numerator value of the fractional baud rate divide register.
• M the 2-bit multipier value of the fractional baud rate divide register.
• FBEN (Fractional Baudrate Generator Enable) is set to enable the fractional baudrate generator feature.

Rx & Tx Register Group

• COMTX/RX (Transmit and Receive Register) when receiving, contains the oldest character received. When transmitting, it contains the newest character to be transmitted.

Scratch Pad Group

• COMSCR (Scratch Pad Register) has no effect on the UART operation. It is used for temporary storage.

Network Address Group

• COMADR (Network Address Register) When the UART is enabled in network addressable mode, this register contains the address to be checked for by the UART.

Modem Control Group

• COMCON1 (Modem Control Register) contains the DTR, RTS and Loopback modem controls.
• DTR Control (Data Terminal Ready Control) is the DTR modem output level.
• LOOPBACK (Loopback Mode) is set to perform diagnostic loopback testing.

Modem Status Group

• COMSTA1 (Modem Status Register) contains the following status from the modem input signals:
• DCTS (Delta Clear to Send) is set when the state of modem input CTS changes.
• DDSR (Delta Data Set Ready) is set when the state of modem input DSR changes.
• TERI (Trailing Edge Ring Indicator) is set when a low-to-high transition occurs on the RI input.
• DDCD (Delta Data Carrier Detect) is set when the state of modem input DCD changes.
• CTS (Clear To Send) is the complement of the CTS input signal.
• DSR (Data Set Ready) is the complement of the CTS input signal.
• RI (Ring Indicator) is the complement of the CTS input signal.
• DCD (Data Carrier Detect) is the complement of the CTS input signal.

Network IE Group

• COMIEN1 (Network Enable Register) contains the combined information for the following:
• NAB (Network Address Bit) is set to transfer the address of the slave.
• NABP (Network Address, Interrupt Polarity)
• ETD (Transmitter Pin Driver Enable) is set to configure the SOUT pin as an output in slave or multi-master mode.
• E9BD (Enable 9-Bit Data Words) is set for 9-bit data and cleared for 8-bit data.
• ENI (Enable Network Interrupt) is set to enable netrok interrupts.
• E9BR (Enable 9-Bit Receive) is set to receive 9-bit data.
• ENAM (Enable Network Address Mode) is set to enable network address mode.

Network Interrupt ID Group

• COMIID1 (Network Interrupt Register) contains the interrupt identifier value.
• ID (Identifier) display the interrupt identifier in text format.