Peripheral Simulation

For Atmel AT91F40816 — Watchdog Timer

Simulation support for this peripheral or feature is comprised of:

• Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

Watchdog Timer Dialog

The Watchdog Timer Dialog shows the current state of the on-chip Watchdog Timer. You can change watchdog settings using the controls in this dialog.

Overflow Mode Group

• WD_OMR (Overflow Mode Register) holds the parameters that control what happens when a timer overflow occurs. They are:
• WDEN (Watch Dog Enable) enables the watchdog timer.
• RSTEN generates and internal reset when an overflow occurs.
• IRQEN generates an interrupt when an overflow occurs.
• EXTEN generates a pulse on pin NWDOVF when an overflow occurs.

Clock Mode Group

• WD_CMR (Clock Mode Register) holds the parameters that select the watch dog timer clock and countdown timer values. They are:
• WDCLKS (Clock Selection) selects the time base for the watch dog timer clock.
• HPCV (High Preload Counter Value) is the value loaded into the watch dog timer counter when it is restarted.

Control Group

• WD_CR (Control Register) storing the Restart Key value in this register restarts the watch dog timer.

Status Group

• WD_SR (Status Register) hold the WDOVF value.
• WDOVF (Watchdog Overflow) is set when a watchdog timer overflow occurs.