Peripheral Simulation

For Atmel AT91M43300 — Timer Counter Block 1 (3 Channels)

Simulation support for this peripheral or feature is comprised of:

• Dialog boxes which display and allow you to change peripheral configuration.

These simulation capabilities are described below.

Timer Counter Block 1 Dialog

The Timer/Counter Block 1 Dialog displays and changes the settings associated with Timer/Counter Block 1. Timer/counters perform various event counting and measurement tasks.

Block & Control Mode

• SYNC creates a synchronization input signal.
• TC0XC0S defines the external clock input signal for this Timer/Counter.

Selected Channel Control

• TC0_CCR displays the Timer/Counter Channel Control Register.
• SWTRG performs a software trigger.
• CLKDIS disables the clock.
• CLKEN enables the clock.

Selected Channel Mode

• TC0CMR displays the Timer/Counter Capture Mode Register.
• WAVE enables Waveform mode.
• CPCTRG resets the counter and starts the clock.
• TCCLKS selects the source and time base of the clock signal.
• CKLI (Clock Invert) increments the falling edge of the clock.
• BURST gates the clock by a selected external signal.
• ABETRG (TIOA/TIOB External Trigger) uses TIOA as an external trigger when checked. Uses TIOB when not checked.
• LDBSTOP stops the counter clock when RB loading occurs.
• LDBDIS disables the counter clock when RB loading occurs.
• ETRGEDG selects the rising edge, falling edge or both for an external trigger.
• LDRA selects loading of register A on the rising edge of TIOA, falling edge or both.
• LDRB selects loading of register B on the rising edge of TIOA, falling edge or both.

Selected Channel Counter Value & Compare/Capture Registers

• TC0_CV holds the Timer/Counter value.
• TC0_RA holds the Timer/Counter Register A value.
• TC0_RB holds the Timer/Counter Register B value.
• TC0_RC holds the Timer/Counter Register C value.

Selected Channel Interrupt Mask & Status

• TC0_IMR displays the Timer/Counter Interrupt Mask Register.
• TC0_SR displays the Timer/Counter Status Register.
• MTIOB (TIOB Mirror) if set, TIOB is high and if WAVE is set, TIOB is driven high.
• MTIOA (TIOA Mirror) if set, TIOA is high and if WAVE is set, TIOA is driven high.
• CLKSTA (Clock Status) if set, clock is enabled.
• ETRG set if an external trigger occurred after the last read of the Status Register.
• LDRB set if register B loading occurred after the last read of the Status Register.
• LDRA set if register A loading occurred after the last read of the Status Register.
• CPCS set if register C compare occurred after the last read of the Status Register.
• CPBS set if register B compare occurred after the last read of the Status Register.
• CPAS set if register A compare occurred after the last read of the Status Register.
• LOVRS set if registers A or B were loaded 2 or more times with no read after the last read of the Status Register.
• COVFS set if a counter overflowed since the last read of the Status Register.

I/O Pins

• TCLK0 Timer 0 Clock signal input.
• TCLK1 Timer 1 Clock signal input.
• TCLK2 Timer 2 Clock signal input.
• TIOA0 Timer 0 Signal A input.
• TIOA1 Timer 1 Signal A input.
• TIOA2 Timer 2 Signal A input.
• TIOB0 Timer 0 Signal B input.
• TIOB1 Timer 1 Signal B input.
• TIOB2 Timer 2 Signal B input.