Peripheral Simulation

For Silicon Laboratories, Inc. C8051F125 — Power Saving Modes (Idle and Power Down)

Simulation support for this peripheral or feature is comprised of:

• VTREGs (Virtual Target Registers) which support I/O with the peripheral.
• Example code which helps you get started quickly.

These simulation capabilities are described below.

RST VTREG
Data Type: bit

RST simulates the reset pin of the MCU. This pin is bi-directional, allowing an external reset input or a Power On Reset (POR), generated internally, to be output on this pin.

Idle Mode Example Program

The Keil Debugger fully simulates the effects of Idle Mode. When your target program initiates Idle Mode program execution stops until the next interrupt is triggered. The following example code shows how to enter Idle Mode.

while (1)          // Repeat Forever
  {
  PCON |= 0x01;    // Enter IDLE Mode
  count++;         // Interrupt Wakes-up MCU
  }

Power Down Mode Example Program

The Keil Debugger fully simulates the effects of Power Down Mode. When your target program initiates Power Down Mode program execution stops until the next external interrupt is triggered or until the MCU is reset. The following example code shows how to enter Power Down Mode.

while (1)          // Repeat Forever
  {
  PCON |= 0x02;    // Enter Power Down Mode
  count++;         // External Interrupt or Reset Wakes-up MCU
  }