Peripheral Simulation

For Synopsys DW-8051 — 4 Clocks per Machine Cycle

Simulation support for this peripheral or feature is comprised of:

Accurate simulation of special on-chip features.

These simulation capabilities are described below.

4 Clocks per Machine Cycle

The standard 8051 MCU requires 12 clocks per machine cycle. The DW8051 IP-Core is a high-speed 8051-compatible core that requires only 4 clocks per machine cycle. As a result, the fastest instruction on a standard 8051 will execute 3 times faster on the DS89C420 MCU.

Get more information about the
Peripheral Simulation Capabilities
of the µVision Debugger.