Peripheral Simulation

For Infineon C511-R — PDATA Memory

Simulation support for this peripheral or feature is comprised of:

• VTREGs (Virtual Target Registers) which support I/O with the peripheral.

These simulation capabilities are described below.

PPAGE VTREG
Data Type: unsigned long

The PPAGE VTREG allows you to specify the address of the page of XDATA memory that is used for PDATA memory accesses (using the MOVX @R0/@R1 instructions). You may specify that PDATA memory accesses use a specific value for the upper address byte. For example,

PPAGE=0x11

causes PDATA memory accesses to use XDATA from 0x1100-0x11FF. You may specify that PDATA memory accesses get the upper address byte from a specific SFR. For example,

PPAGE=D:0xA0

causes PDATA memory accesses to get the upper address byte from the P2 SFR. By default, PPAGE is set to 0xFFFFFFFF. This value causes PDATA memory accesses to use the default SFR (usually this is P2) for the upper address byte.