/*-------------------------------------------------------------------------- GC80C510_SO20I.H (ver 1.0) Header file for the GenCore Turbo GC80C510 Series GC87C510A0-SP20I : 20 Pins SPDIP Package GC87C510A0-SO20I : 20 Pins SOIC Package GC87C510A0-SP16I : 16 Pins SPDIP Package GC87C510A0-SO16I : 16 Pins SOIC Package GC87C510A0-SP14I : 14 Pins SPDIP Package GC87C510A0-SO14I : 14 Pins SOIC Package GC87C510A0-SP8I : 8 Pins SPDIP Package GC87C510A0-SO8I : 8 Pins SOIC Package Copyright (c) 2003-2004 GenCore Technology, Inc. All rights reserved. --------------------------------------------------------------------------*/ #ifndef GC80C510_HEADER_FILE #define GC80C510_HEADER_FILE 1 /*------------------------------------------------ Byte Registers ------------------------------------------------*/ sfr P0 = 0x80; /* Port 0 */ sfr p0 = 0x80; /* Port 0 */ sfr SP = 0x81; /* Stack Pointer */ sfr sp = 0x81; /* Stack Pointer */ sfr DPL = 0x82; /* Data Pointer Low */ sfr dpl = 0x82; /* Data Pointer Low */ sfr DPH = 0x83; /* Data Pointer High */ sfr dph = 0x83; /* Data Pointer High */ sfr PCON = 0x87; /* Power Control */ sfr pcon = 0x87; /* Power Control */ sfr TCON = 0x88; /* Timer 0/1 Control */ sfr tcon = 0x88; /* Timer 0/1 Control */ sfr TMOD = 0x89; /* Timer 0/1 Mode Control */ sfr tmod = 0x89; /* Timer 0/1 Mode Control */ sfr TL0 = 0x8A; /* Timer 0 Low Byte */ sfr tl0 = 0x8A; /* Timer 0 Low Byte */ sfr TL1 = 0x8B; /* Timer 1 Low Byte */ sfr tl1 = 0x8B; /* Timer 1 Low Byte */ sfr TH0 = 0x8C; /* Timer 0 High Byte */ sfr th0 = 0x8C; /* Timer 0 High Byte */ sfr TH1 = 0x8D; /* Timer 1 High Byte */ sfr th1 = 0x8D; /* Timer 1 High Byte */ sfr P1 = 0x90; /* Port 1 */ sfr p1 = 0x90; /* Port 1 */ sfr EXIF = 0x91; /* External Interrupt Flag */ sfr exif = 0x91; /* External Interrupt Flag */ sfr SCON = 0x98; /* Serial Port Control */ sfr scon = 0x98; /* Serial Port Control */ sfr SBUF = 0x99; /* Serial Data Buffer */ sfr sbuf = 0x99; /* Serial Data Buffer */ sfr P2 = 0xA0; /* Port 2 */ sfr p2 = 0xA0; /* Port 2 */ sfr IE = 0xA8; /* Interrupt Enable */ sfr ie = 0xA8; /* Interrupt Enable */ sfr IP = 0xB8; /* Interrupt Priority Low */ sfr ip = 0xB8; /* Interrupt Priority Low */ sfr OSCICN = 0xBE; /* Oscillator Control */ sfr oscicn = 0xBE; /* Oscillator Control */ sfr PMR = 0xC4; /* Power Management Control */ sfr pmr = 0xC4; /* Power Management Control */ sfr STATUS = 0xC5; /* Crystal Status */ sfr status = 0xC5; /* Crystal Status */ sfr PSW = 0xD0; /* Program Status Word */ sfr psw = 0xD0; /* Program Status Word */ sfr P0TYPE = 0xD4; /* Port 0 Type */ sfr p0type = 0xD4; /* Port 0 Type */ sfr P1TYPE = 0xD5; /* Port 1 Type */ sfr p1type = 0xD5; /* Port 1 Type */ sfr P2TYPE = 0xD6; /* Port 2 Type */ sfr p2type = 0xD6; /* Port 2 Type */ sfr WDCON = 0xD8; /* Watchdog & Power Status */ sfr wdcon = 0xD8; /* Watchdog & Power Status */ sfr PWMCON = 0xDC; /* PWM Control */ sfr pwmcon = 0xDC; /* PWM Control */ sfr PWM0CON = 0xDC; /* PWM Control */ sfr pwm0con = 0xDC; /* PWM Control */ sfr PWMD = 0xDE; /* PWM Duty Data */ sfr pwmd = 0xDE; /* PWM Duty Data */ sfr PWM0D = 0xDE; /* PWM Duty Data */ sfr pwm0d = 0xDE; /* PWM Duty Data */ sfr ACC = 0xE0; /* Accumulator : A Register */ sfr acc = 0xE0; /* Accumulator : A Register */ sfr ADCSELH = 0xE1; /* AD Clock and Port Control High */ sfr adcselh = 0xE1; /* AD Clock and Port Control High */ sfr ADCSEL = 0xE2; /* AD Clock and Port Control */ sfr adcsel = 0xE2; /* AD Clock and Port Control */ sfr ALTSEL = 0xE3; /* Alternative Funcrion Selection */ sfr altsel = 0xE3; /* Alternative Funcrion Selection */ sfr P0SEL = 0xE4; /* Port 0 Pull-up Control */ sfr p0sel = 0xE4; /* Port 0 Pull-up Control */ sfr P1SEL = 0xE5; /* Port 1 Pull-up Control */ sfr p1sel = 0xE5; /* Port 1 Pull-up Control */ sfr P2SEL = 0xE6; /* Port 2 Pull-up Control */ sfr p2sel = 0xE6; /* Port 2 Pull-up Control */ sfr EIE = 0xE8; /* Extended Interrupy Enable */ sfr eie = 0xE8; /* Extended Interrupy Enable */ sfr ADCR = 0xEE; /* ADC Result Value [9:2] */ sfr adcr = 0xEE; /* ADC Result Value [9:2] */ sfr ADCON = 0xEF; /* ADC Control, ADC Result Value [1:0] */ sfr adcon = 0xEF; /* ADC Control, ADC Result Value [1:0] */ sfr B = 0xF0; /* Second Accumulator : B Register */ sfr b = 0xF0; /* Second Accumulator : B Register */ sfr P0DIR = 0xF4; /* Port 0 Direction */ sfr p0dir = 0xF4; /* Port 0 Direction */ sfr P1DIR = 0xF5; /* Port 1 Direction */ sfr p1dir = 0xF5; /* Port 1 Direction */ sfr P2DIR = 0xF6; /* Port 2 Direction */ sfr p2dir = 0xF6; /* Port 2 Direction */ sfr EIP = 0xF8; /* Extended Interrupt Priority */ sfr eip = 0xF8; /* Extended Interrupt Priority */ /*------------------------------------------------ P0 (80h) Bit Register ------------------------------------------------*/ sbit P0_0 = 0x80; sbit p0_0 = 0x80; sbit P0_1 = 0x81; sbit p0_1 = 0x81; sbit P0_2 = 0x82; sbit p0_2 = 0x82; sbit P0_3 = 0x83; sbit p0_3 = 0x83; sbit P0_4 = 0x84; sbit p0_4 = 0x84; sbit P0_5 = 0x85; sbit p0_5 = 0x85; sbit P0_6 = 0x86; sbit p0_6 = 0x86; sbit P0_7 = 0x87; sbit p0_7 = 0x87; sbit P00 = 0x80; sbit p00 = 0x80; sbit P01 = 0x81; sbit p01 = 0x81; sbit P02 = 0x82; sbit p02 = 0x82; sbit P03 = 0x83; sbit p03 = 0x83; sbit P04 = 0x84; sbit p04 = 0x84; sbit P05 = 0x85; sbit p05 = 0x85; sbit P06 = 0x86; sbit p06 = 0x86; sbit P07 = 0x87; sbit p07 = 0x87; sbit INT0 = 0x80; /* External interrupt 0_b */ sbit int0 = 0x80; /* External interrupt 0_b */ sbit PWM = 0x80; /* PWM */ sbit pwm = 0x80; /* PWM */ sbit TVO = 0x80; /* TVO */ sbit tvo = 0x80; /* TVO */ sbit INT1 = 0x81; /* External interrupt 1_b */ sbit int1 = 0x81; /* External interrupt 1_b */ sbit RXD = 0x81; /* Serial data input */ sbit rxd = 0x81; /* Serial data input */ sbit INT2 = 0x82; /* External interrupt 2 */ sbit int2 = 0x82; /* External interrupt 2 */ sbit TXD = 0x82; /* Serial data output */ sbit txd = 0x82; /* Serial data output */ sbit INT3 = 0x83; /* External interrupt 3_b */ sbit int3 = 0x83; /* External interrupt 3_b */ /*------------------------------------------------ PCON (87h) Bit Values ------------------------------------------------*/ #define IDL_ 0x01 /* IDLE Mode Bit */ #define PD_ 0x02 /* Power Down Mode Bit */ #define STOP_ 0x02 /* Alternate definition */ #define GF0_ 0x04 /* General Purpose Flag */ #define GF1_ 0x08 /* General Purpose Flag */ #define POF_ 0x10 /* Power Off Flag. 1 (Default) When Power On, this bit will be set by H/W */ #define SMOD1_ 0x80 /* Timer 1 Baud Rate Double in UART Mode 1. */ /*------------------------------------------------ TCON (88h) Bit Register ------------------------------------------------*/ sbit IT0 = 0x88; /* External Interrupt 0 Type Select */ sbit it0 = 0x88; /* External Interrupt 0 Type Select */ sbit IE0 = 0x89; /* External Interrupt 0 Flag */ sbit ie0 = 0x89; /* External Interrupt 0 Flag */ sbit IT1 = 0x8A; /* External Interrupt 1 Type Select */ sbit it1 = 0x8A; /* External Interrupt 1 Type Select */ sbit IE1 = 0x8B; /* External Interrupt 1 Flag */ sbit ie1 = 0x8B; /* External Interrupt 1 Flag */ sbit TR0 = 0x8C; /* Timer 0 Run Enable */ sbit tr0 = 0x8C; /* Timer 0 Run Enable */ sbit TF0 = 0x8D; /* Timer 0 Overflow Flag */ sbit tf0 = 0x8D; /* Timer 0 Overflow Flag */ sbit TR1 = 0x8E; /* Timer 1 Run Enable */ sbit tr1 = 0x8E; /* Timer 1 Run Enable */ sbit TF1 = 0x8F; /* Timer 1 Overflow Flag */ sbit tf1 = 0x8F; /* Timer 1 Overflow Flag */ /*------------------------------------------------ TMOD (89h) Bit Values ------------------------------------------------*/ #define T0_M0_ 0x01 /* T0_M[1:0] : Timer 0 Mode Select. */ #define T0_M1_ 0x02 /* [0,0] = Mode 0, 13-bit T/C [0,1] = Mode 1, 16-bit T/C [1,0] = Mode 2, 8-bit T/C with Auto-reload [1,1] = Mode 3, Two 8-bit T/C */ #define T0_CT_ 0x04 /* Timer 0 Counter/Timer Select. 0 = C/T, Timer using Osc. (Default) 1 = C/T, Counter by T0 pin. */ #define T0_GATE_ 0x08 /* Timer 0 Gate Control */ #define T0_MASK_ 0x0F /*------------------------------------------------ P1 (90h) Bit Register ------------------------------------------------*/ sbit P1_0 = 0x90; sbit p1_0 = 0x90; sbit P1_1 = 0x91; sbit p1_1 = 0x91; sbit P1_2 = 0x92; sbit p1_2 = 0x92; sbit P10 = 0x90; sbit p10 = 0x90; sbit P11 = 0x91; sbit p11 = 0x91; sbit P12 = 0x92; sbit p12 = 0x92; /*------------------------------------------------ EXIF (91h) Bit Value ------------------------------------------------*/ #define BGS_ 0x01 /* Band-gap Select. (Default 1) When set, LVD will run in power-down mode. */ #define RGSL_ 0x02 /* 1 (Default) : When wake-up from Power-down mode in XTAL clock, using Ring Oscillator as system clock during 65,536 XTAL clocks */ #define RGMD 0x04 /* Ring Mode : The Value of RGMD is the invert of XTRG 1 = Ring Osc. ON (default) 0 = Ring Osc. off. */ #define XTRG_ 0x08 /* System Clock Selection 0 = System clock is Ring Osc. (Default) 1 = System clock is Crystal Osc. */ #define IE2_ 0x10 /* External Interrupt 2 Flag */ #define IE3_ 0x20 /* External Interrupt 3 Flag_b */ /*------------------------------------------------ SCON (98h) Bit Register ------------------------------------------------*/ sbit RI = 0x98; /* Reception Interrupt Flag */ sbit ri = 0x98; /* Reception Interrupt Flag */ sbit TI = 0x99; /* Transmission Interrupt Flag */ sbit ti = 0x99; /* Transmission Interrupt Flag */ sbit REN = 0x9C; /* Serial Reception Enable */ sbit ren = 0x9C; /* Serial Reception Enable */ /*------------------------------------------------ P2 (A0h) Bit Register ------------------------------------------------*/ sbit P2_0 = 0xA0; sbit p2_0 = 0xA0; sbit P2_1 = 0xA1; sbit p2_1 = 0xA1; sbit P2_2 = 0xA2; sbit p2_2 = 0xA2; sbit P2_3 = 0xA3; sbit p2_3 = 0xA3; sbit P2_4 = 0xA4; sbit p2_4 = 0xA4; sbit P2_5 = 0xA5; sbit p2_5 = 0xA5; sbit P2_6 = 0xA6; sbit p2_6 = 0xA6; sbit P20 = 0xA0; sbit p20 = 0xA0; sbit P21 = 0xA1; sbit p21 = 0xA1; sbit P22 = 0xA2; sbit p22 = 0xA2; sbit P23 = 0xA3; sbit p23 = 0xA3; sbit P24 = 0xA4; sbit p24 = 0xA4; sbit P25 = 0xA5; sbit p25 = 0xA5; sbit P26 = 0xA6; sbit p26 = 0xA6; sbit T0 = 0xA0; /* Timer 0 external input */ sbit t0 = 0xA0; /* Timer 0 external input */ /*------------------------------------------------ IE (A8h) Bit Register ------------------------------------------------*/ /* The each value of IE flags is 0(disable). */ sbit EX0 = 0xA8; /* 1 = EX0 : Enable External Interrupt 0 */ sbit ex0 = 0xA8; /* 1 = EX0 : Enable External Interrupt 0 */ sbit ET0 = 0xA9; /* 1 = ET0 : Enable Timer 0 Interrupt */ sbit et0 = 0xA9; /* 1 = ET0 : Enable Timer 0 Interrupt */ sbit EX1 = 0xAA; /* 1 = EX1 : Enable External Interrupt 1 */ sbit ex1 = 0xAA; /* 1 = EX1 : Enable External Interrupt 1 */ sbit ET1 = 0xAB; /* 1 = ET2 : Enable Timer 1 Interrupt */ sbit et1 = 0xAB; /* 1 = ET2 : Enable Timer 1 Interrupt */ sbit ES = 0xAC; /* 1 = ES : Enable Serial Port Interrupt */ sbit es = 0xAC; /* 1 = ES : Enable Serial Port Interrupt */ sbit EADC = 0xAE; /* 1 = EADC : Enable ADC Interrupt */ sbit eadc = 0xAE; /* 1 = EADC : Enable ADC Interrupt */ sbit EA = 0xAF; /* 1 = EA : Enable All Interrupt */ sbit ea = 0xAF; /* 1 = EA : Enable All Interrupt */ /*------------------------------------------------ IP (B8h) Bit Register ------------------------------------------------*/ sbit PX0 = 0xB8; /* External Interrupt 0 Priority */ sbit px0 = 0xB8; /* External Interrupt 0 Priority */ sbit PT0 = 0xB9; /* Timer 0 Interrypt Priority */ sbit pt0 = 0xB9; /* Timer 0 Interrypt Priority */ sbit PX1 = 0xBA; /* External Interrupy 1 Priority */ sbit px1 = 0xBA; /* External Interrupy 1 Priority */ sbit PT1 = 0xBB; /* Timer 1 Interrupt Priority */ sbit pt1 = 0xBB; /* Timer 1 Interrupt Priority */ sbit PS = 0xBC; /* Serial Port Interrupt Priority */ sbit ps = 0xBC; /* Serial Port Interrupt Priority */ sbit PT2 = 0xBD; /* Timer 2 Interrupy Priority */ sbit pt2 = 0xBD; /* Timer 2 Interrupy Priority */ sbit PADC = 0xBE; /* ADC Interrupt Priority */ sbit padc = 0xBE; /* ADC Interrupt Priority */ /*------------------------------------------------ OSCIN (BEh) Bit Value ------------------------------------------------*/ #define DIV0_ 0x01 /* DIV[1:0] : Ring Oscillator Divider */ #define DIV1_ 0x02 /* [0,0] = 4MHz /1 = 4MHz [0,1] = 4MHz /2 = 2MHz [1,0] = 4MHz /4 = 1MHz [1,1] = 4MHz /8 = 500kHz*/ #define RINGON_ 0x04 /* 1 = RINGON : Internal Ring Osc. is running. (Default) 0 = RINGON : Internal Ring Osc. is killed. Don't clear RINGON when XTRG = 1 (Sys CLK = Crystal Osc). */ /*------------------------------------------------ PMR (C4h) Bit Value ------------------------------------------------*/ #define XTOFF_ 0x08 /* 0 = XTOFF : External Crystal Osc. is running. (Default) 1 = XTOFF : External Crystal Osc. is killed. Don't set XTOFF when XTRG = 1 (Sys CLK = Crystal Osc). */ /*------------------------------------------------ PSW (D0h) Bit Register ------------------------------------------------*/ sbit F1 = 0xD1; /* User Flag 1 */ sbit f1 = 0xD1; /* User Flag 1 */ sbit OV = 0xD2; /* Overflow Flag */ sbit ov = 0xD2; /* Overflow Flag */ sbit RS0 = 0xD3; /* RS1, RS0 : Register Bank Select */ sbit rs0 = 0xD3; /* RS1, RS0 : Register Bank Select */ sbit RS1 = 0xD4; /* [0,0] : Bank 0, [0,1] = Bank 1 */ /* [1,0] : Bank 2, [1,1] = Bank 3 */ sbit rs1 = 0xD4; /* [0,0] : Bank 0, [0,1] = Bank 1 */ /* [1,0] : Bank 2, [1,1] = Bank 3 */ sbit F0 = 0xD5; /* User Flag 0 */ sbit f0 = 0xD5; /* User Flag 0 */ sbit AC = 0xD6; /* Auxiliary Carry Flag */ sbit ac = 0xD6; /* Auxiliary Carry Flag */ sbit CY = 0xD7; /* Carry Flag */ sbit cy = 0xD7; /* Carry Flag */ /*------------------------------------------------ P0TYPE (D4h) Bit Value ------------------------------------------------*/ #define P0TY6_ 0x40 /* Port0 push-pull/open-drain control */ #define P0TY5_ 0x20 /* 0 = Push-pull (Default) */ #define P0TY4_ 0x10 /* 1 = Open-drain */ #define P0TY3_ 0x08 #define P0TY2_ 0x04 #define P0TY1_ 0x02 #define P0TY0_ 0x01 /*------------------------------------------------ P1TYPE (D5h) Bit Value ------------------------------------------------*/ #define P1TY1_ 0x02 /* Port1 push-pull/open-drain control */ #define P1TY0_ 0x01 /* 0 = Push-pull (Default) */ /* 1 = Open-drain */ /*------------------------------------------------ P2TYPE (D6h) Bit Value ------------------------------------------------*/ #define P2TY6_ 0x40 /* Port2 push-pull/open-drain control */ #define P2TY5_ 0x20 /* 0 = Push-pull (Default) */ #define P2TY4_ 0x10 /* 1 = Open-drain */ #define P2TY3_ 0x08 #define P2TY2_ 0x04 #define P2TY1_ 0x02 #define P2TY0_ 0x01 /*------------------------------------------------ WDCON (D8h) Bit Register ------------------------------------------------*/ sbit RWT = 0xD8; /* Restart Watchdog Timer */ sbit rwt = 0xD8; /* Restart Watchdog Timer */ sbit EWT = 0xD9; /* Watchdog Timer Reset Enable */ sbit ewt = 0xD9; /* Watchdog Timer Reset Enable */ sbit WTRF = 0xDA; /* Watchdog Timer Reset Flag */ sbit wtrf = 0xDA; /* Watchdog Timer Reset Flag */ sbit WDIF = 0xDB; /* Watchdog Timer Interrupt Flag */ sbit wdif = 0xDB; /* Watchdog Timer Interrupt Flag */ sbit PFI = 0xDC; /* Power-fail Interrupt Flag */ sbit pfi = 0xDC; /* Power-fail Interrupt Flag */ sbit EPFI = 0xDD; /* Enable Power-fail Interrupt */ sbit epfi = 0xDD; /* Enable Power-fail Interrupt */ sbit WD0 = 0xDE; /* WD[1:0] Watchdog Timer Mode Select */ sbit wd0 = 0xDE; /* WD[1:0] Watchdog Timer Mode Select */ sbit WD1 = 0xDF; /* [0,0]= 1 X 2^16 clks(Interrupt) + 256 clks(Reset) [0,1]= 4 X 2^16 clks(Interrupt) + 256 clks(Reset) [1,0]= 16 X 2^16 clks(Interrupt) + 256 clks(Reset) [1,1]= 32 X 2^16 clks(Interrupt) + 256 clks(Reset) */ sbit wd1 = 0xDF; /* [0,0]= 1 X 2^16 clks(Interrupt) + 256 clks(Reset) [0,1]= 4 X 2^16 clks(Interrupt) + 256 clks(Reset) [1,0]= 16 X 2^16 clks(Interrupt) + 256 clks(Reset) [1,1]= 32 X 2^16 clks(Interrupt) + 256 clks(Reset) */ /*------------------------------------------------ PWMCON (DCh) Bit Value ------------------------------------------------*/ #define RUN_P0_ 0x01 /* Counter Start Enable */ #define CLR_P0_ 0x02 /* Counter Reset Enable. Clear by H/W */ #define PWMF_ 0x04 /* PWM Interrupt Flag */ #define PS0_P_ 0x10 /* [PS2_P0, PS1_P0, PS0_P0] :*/ #define PS1_P_ 0x20 /* Prescaled Clock Selection */ #define PS2_P_ 0x40 /* [0,0,0] = Fosc, [0,0,1] = Fosc/2, [0,1,0] = Fosc/4, [0,1,1] = Fosc/8, [1,0,0] = Fosc/16, [1,0,1] = Fosc/32, [1,1,0] = Fosc/64, [1,1,1] = Fosc/128, */ #define P0SEL_ 0x80 /* PWM Output Enable to P0.6 */ /* How to Enable PWM Output ------------------------ [How to Enable PWM Output to P0.0] Refer to ALTSEL (E3h) Setting. 0 = PWM00 : PWM Output Disable to P0.0 (Default) 1 = PWM00 : PWM Output Enable to P0.0 [How to Enable PWM Output to P0.6] Refer to PWMCON (DCh) Setting. 0 = P0SEL : PWM Output Disable to P0.6 (Default) 1 = P0SEL : PWM Output Enable to P0.6 */ /*------------------------------------------------ ALTSEL (E3h) Bit Value ------------------------------------------------*/ #define TX_ 0x04 /* 1 = UART TX Data Output to P0.2 */ /* 0 = TX : as I/O(P0.2). (Default) */ #define TVO_ 0x08 /* 1 = Timer0 Overflow Clock to P0.0 */ /* 0 = TVO : as I/O(P0.8). (Default) */ #define PWM00_ 0x10 /* PWM Output Enable to P0.0 */ /* How to Enable PWM Output ------------------------ [How to Enable PWM Output to P0.0] Refer to ALTSEL (E3h) Setting. 0 = PWM00 : PWM Output Disable to P0.0 (Default) 1 = PWM00 : PWM Output Enable to P0.0 [How to Enable PWM Output to P0.6] Refer to PWMCON (DCh) Setting. 0 = P0SEL : PWM Output Disable to P0.6 (Default) 1 = P0SEL : PWM Output Enable to P0.6 */ #define CLO_ 0x20 /* 1 = CLO : System Clock Output to P2.6 */ /* 0 = CLO : as I/O(P2.6) (Default) */ #define IORSTEN_ 0x40 /* 1 = IORSTEN : RESETB -> as I/O(P1.2).*/ /* 0 = IORSTEN : RESETB Input (Default). */ #define IOXEN_ 0x80 /* 1 = IOXEN : XTAL1 & XTAL2 -> as I/Os(P1[1:0])*/ /* 0 = IOXEN : XTAL1 & XTAL2 Inputs (Default) */ /*------------------------------------------------ ADCSEL (E2h) Bit Value ------------------------------------------------*/ // Before setting the CH[3:0], clear CH[3:0] and then setting CH[3:0] #define CH0_ 0x01 /* CH[3:0] : ADC Channel Selector */ #define CH1_ 0x02 /* [0,0,0,0] = ADC0, [0,0,0,1] = ADC1, */ #define CH2_ 0x04 /* [0,0,1,0] = ADC2, [0,0,1,1] = ADC3, */ #define CH3_ 0x08 /* [0,1,0,0] = ADC4, [0,1,0,1] = ADC5, [0,1,1,0] = ADC6, [0,1,1,1] = ADC7, [1,0,0,0] = ADC8, [1,0,0,1] = ADC9, [1,0,1,0] = ADC10, or [1,0,1,1] = ADC11 is selected */ // ADC0B~11B : Default Flag = 1, Select = 0. #define ADC0B_ 0xEF /* 1 = ADC0B in ADCSEL(E2h). Port 0.1 */ #define ADC1B_ 0xDF /* 1 = ADC1B in ADCSEL. Port 0.2 */ #define ADC2B_ 0xBF /* 1 = ADC2B in ADCSEL. Port 0.3 */ #define ADC3B_ 0x7F /* 1 = ADC3B in ADCSEL. Port 0.4 */ /*------------------------------------------------ ADCSELH (E1h) Bit Value ------------------------------------------------*/ #define ADC4B_ 0xFE /* 1 = ADC4B in ADCSELH(E1h). Port 0.5 */ #define ADC5B_ 0xFD /* 1 = ADC5B in ADCSELH. Port 0.6 */ #define ADC6B_ 0xFB /* 1 = ADC6B in ADCSELH. Port 0.7 */ #define ADC7B_ 0xF7 /* 1 = ADC7B in ADCSELH. Port 2.6 */ #define ADC8B_ 0xEF /* 1 = ADC8B in ADCSELH. Port 2.5 */ #define ADC9B_ 0xDF /* 1 = ADC9B in ADCSELH. Port 2.4 */ #define ADC10B_ 0xBF /* 1 = ADC10B in ADCSELH. Port 2.3 */ #define ADC11B_ 0x7F /* 1 = ADC11B in ADCSELH. Port 2.2 */ /*------------------------------------------------ EIE (E8h) Bit Register ------------------------------------------------*/ sbit EX2 = 0xE8; /* External 2 Interrupt Enable */ sbit ex2 = 0xE8; /* External 2 Interrupt Enable */ sbit EX3 = 0xE9; /* External 3 Interrupt Enable */ sbit ex3 = 0xE9; /* External 3 Interrupt Enable */ sbit EWDT = 0xEC; /* Watchdog Interrupt Enable */ sbit ewdt = 0xEC; /* Watchdog Interrupt Enable */ sbit EPWM = 0xED; /* PWM Interrupt Enable */ sbit epwm = 0xED; /* PWM Interrupt Enable */ /*------------------------------------------------ ADCON (EFh) Bit Value ------------------------------------------------*/ #define ADIV_ 0x04; /* 0 = ADIV in ADCON(EFh) : Fosc/2. (Default) */ /* 1 = ADIV in ADCON : PWM Clock as FADC */ #define AVREF_ 0x80; /* 0 = AVREF in ADCON : Vref using VDD.(Default) */ /* 1 = AVREF in ADCON : Vref using Port 0.3 */ #define ADCF_ 0x10 /* ADC Interrupt Flag. Must be Cleared by S/W */ #define AD_END_ 0x20 /* Current ADC Status. (Read Only) 1 = ADC is END (Default). 0 = ADC is running now */ #define AD_REQ_ 0x40 /* ADC Start Enable. */ /* Clear when AD_END goes to 1 from 0. */ #define AD_EN_ 0x80 /* ADC Ready Enable */ /*------------------------------------------------ EIP (F8h) Bit Register ------------------------------------------------*/ sbit PX2 = 0xF8; /* External 2 Interrupt Priority Bit */ sbit px2 = 0xF8; /* External 2 Interrupt Priority Bit */ sbit PX3 = 0xF9; /* External 3 Interrupt Priority Bit */ sbit px3 = 0xF9; /* External 3 Interrupt Priority Bit */ sbit PWDT = 0xFC; /* Watchdog Interrupt Priority Bit */ sbit pwdt = 0xFC; /* Watchdog Interrupt Priority Bit */ sbit PPWM = 0xFD; /* PWM Interrupt Priority Bit */ sbit ppwm = 0xFD; /* PWM Interrupt Priority Bit */ /*------------------------------------------------ ACC (A; E0h) Bit Register ------------------------------------------------*/ sbit ACC_0 = 0xE0; sbit acc_0 = 0xE0; sbit ACC_1 = 0xE1; sbit acc_1 = 0xE1; sbit ACC_2 = 0xE2; sbit acc_2 = 0xE2; sbit ACC_3 = 0xE3; sbit acc_3 = 0xE3; sbit ACC_4 = 0xE4; sbit acc_4 = 0xE4; sbit ACC_5 = 0xE5; sbit acc_5 = 0xE5; sbit ACC_6 = 0xE6; sbit acc_6 = 0xE6; sbit ACC_7 = 0xE7; sbit acc_7 = 0xE7; sbit ACC0 = 0xE0; sbit acc0 = 0xE0; sbit ACC1 = 0xE1; sbit acc1 = 0xE1; sbit ACC2 = 0xE2; sbit acc2 = 0xE2; sbit ACC3 = 0xE3; sbit acc3 = 0xE3; sbit ACC4 = 0xE4; sbit acc4 = 0xE4; sbit ACC5 = 0xE5; sbit acc5 = 0xE5; sbit ACC6 = 0xE6; sbit acc6 = 0xE6; sbit ACC7 = 0xE7; sbit acc7 = 0xE7; /*------------------------------------------------ P0DIR (F4h) Bit Value ------------------------------------------------*/ #define P0DIR7_ 0x80 /* Port0 input/output control */ #define P0DIR6_ 0x40 /* 1 = Input (Default) */ #define P0DIR5_ 0x20 /* 0 = Output */ #define P0DIR4_ 0x10 #define P0DIR3_ 0x08 #define P0DIR2_ 0x04 #define P0DIR1_ 0x02 #define P0DIR0_ 0x01 /*------------------------------------------------ P1DIR (F5h) Bit Value ------------------------------------------------*/ #define P1DIR2_ 0x04 /* Port1 input/output control */ #define P1DIR1_ 0x02 /* 1 = Input (Default) */ #define P1DIR0_ 0x01 /* 0 = Output */ /*------------------------------------------------ P2DIR (F6h) Bit Value ------------------------------------------------*/ #define P2DIR6_ 0x40 /* Port2 input/output control */ #define P2DIR5_ 0x20 /* 1 = Input (Default) */ #define P2DIR4_ 0x10 /* 0 = Output */ #define P2DIR3_ 0x08 #define P2DIR2_ 0x04 #define P2DIR1_ 0x02 #define P2DIR0_ 0x01 /*------------------------------------------------ Interrupt Vectors: Interrupt Address = (Number * 8) + 3 ------------------------------------------------*/ #define IE0_VECTOR 0 /* 0x03 External Interrupt 0 */ #define TF0_VECTOR 1 /* 0x0B Timer 0 */ #define IE1_VECTOR 2 /* 0x13 External Interrupt 1 */ #define TF1_VECTOR 3 /* 0x1B Timer 1 */ #define SIO_VECTOR 4 /* 0x23 Serial Port */ #define ADC_VECTOR 7 /* 0x3B ADC */ #define IE2_VECTOR 8 /* 0x43 External Interrupt 2 */ #define IE3_VECTOR 9 /* 0x4B External Interrupt 3 */ #define WDT_VECTOR 12 /* 0x63 Interrupt Watchdog Timer */ #define PWM_VECTOR 13 /* 0x6B Interrupt PWM */ /*------------------------------------------------ Register Banks ------------------------------------------------*/ #define REGISTER_BANK_0 0 /* Register Bank 0 */ #define REGISTER_BANK_1 1 /* Register Bank 1 */ #define REGISTER_BANK_2 2 /* Register Bank 2 */ #define REGISTER_BANK_3 3 /* Register Bank 3 */ /*----------------------------------------------*/ #endif