/** ****************************************************************************** * @file stm32f2xx.h * @author MCD Application Team * @version V1.0.0 - edited by Keil * @date 18-April-2011 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F2xx devices. * * The file is the unique include file that the application programmer * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The device used in the target application * - To use or not the peripheral’s drivers in application code(i.e. * code will be based on direct access to peripheral’s registers * rather than drivers API), this option is controlled by * "#define USE_STDPERIPH_DRIVER" * - To change few application-specific parameters such as the HSE * crystal frequency * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripheral’s registers hardware * ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * *

© COPYRIGHT 2011 STMicroelectronics

****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f2xx * @{ */ #ifndef __STM32F2xx_H #define __STM32F2xx_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /** @addtogroup Library_configuration_section * @{ */ /* Uncomment the line below according to the target STM32 device used in your application */ #if !defined (STM32F2XX) #define STM32F2XX #endif /* Tip: To avoid modifying this file each time you need to switch between these devices, you can define the device in your toolchain compiler preprocessor. */ #if !defined (STM32F2XX) #error "Please select first the target STM32F2XX device used in your application (in stm32f2xx.h file)" #endif #if !defined (USE_STDPERIPH_DRIVER) /** * @brief Comment the line below if you will not use the peripherals drivers. In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers */ /*#define USE_STDPERIPH_DRIVER*/ #endif /* USE_STDPERIPH_DRIVER */ /** * @brief In the following line adjust the value of External High Speed oscillator (HSE) used in your application Tip: To avoid modifying this file each time you need to use different HSE, you can define the HSE value in your toolchain compiler preprocessor. */ #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ /** * @brief In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0600) /*!< Time out for HSE start up */ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ /** * @brief STM32F2Xxx Standard Peripherals Library version number V1.0.0 */ #define __STM32F2XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32F2XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ #define __STM32F2XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F2XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F2XX_STDPERIPH_VERSION ((__STM32F2XX_STDPERIPH_VERSION_MAIN << 24)\ |(__STM32F2XX_STDPERIPH_VERSION_SUB1 << 16)\ |(__STM32F2XX_STDPERIPH_VERSION_SUB2 << 8)\ |(__STM32F2XX_STDPERIPH_VERSION_RC)) /** * @} */ /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** * @brief Configuration of the Cortex-M3 Processor and Core Peripherals */ #define __MPU_PRESENT 1 /*!< STM32F2XX provide an MPU */ #define __NVIC_PRIO_BITS 4 /*!< STM32F2XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ /** * @brief STM32F2XX Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum IRQn { /****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ /****** STM32 specific Interrupt Numbers **********************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ RCC_IRQn = 5, /*!< RCC global Interrupt */ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ FSMC_IRQn = 48, /*!< FSMC global Interrupt */ SDIO_IRQn = 49, /*!< SDIO global Interrupt */ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ UART4_IRQn = 52, /*!< UART4 global Interrupt */ UART5_IRQn = 53, /*!< UART5 global Interrupt */ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ TIM7_IRQn = 55, /*!< TIM7 global interrupt */ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ ETH_IRQn = 61, /*!< Ethernet global Interrupt */ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ USART6_IRQn = 71, /*!< USART6 global interrupt */ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ DCMI_IRQn = 78, /*!< DCMI global interrupt */ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ HASH_RNG_IRQn = 80 /*!< Hash and Rng global interrupt */ } IRQn_Type; /** * @} */ #include "core_cm3.h" #include "system_stm32f2xx.h" #include /** @addtogroup Exported_types * @{ */ /*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ typedef int32_t s32; typedef int16_t s16; typedef int8_t s8; typedef const int32_t sc32; /*!< Read Only */ typedef const int16_t sc16; /*!< Read Only */ typedef const int8_t sc8; /*!< Read Only */ typedef __IO int32_t vs32; typedef __IO int16_t vs16; typedef __IO int8_t vs8; typedef __I int32_t vsc32; /*!< Read Only */ typedef __I int16_t vsc16; /*!< Read Only */ typedef __I int8_t vsc8; /*!< Read Only */ typedef uint32_t u32; typedef uint16_t u16; typedef uint8_t u8; typedef const uint32_t uc32; /*!< Read Only */ typedef const uint16_t uc16; /*!< Read Only */ typedef const uint8_t uc8; /*!< Read Only */ typedef __IO uint32_t vu32; typedef __IO uint16_t vu16; typedef __IO uint8_t vu8; typedef __I uint32_t vuc32; /*!< Read Only */ typedef __I uint16_t vuc16; /*!< Read Only */ typedef __I uint8_t vuc8; /*!< Read Only */ typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; /** * @} */ /** @addtogroup Peripheral_registers_structures * @{ */ /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ } ADC_TypeDef; typedef struct { __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual AND triple modes, Address offset: ADC1 base address + 0x308 */ } ADC_Common_TypeDef; /** * @brief Controller Area Network TxMailBox */ typedef struct { __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ __IO uint32_t TDLR; /*!< CAN mailbox data low register */ __IO uint32_t TDHR; /*!< CAN mailbox data high register */ } CAN_TxMailBox_TypeDef; /** * @brief Controller Area Network FIFOMailBox */ typedef struct { __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ } CAN_FIFOMailBox_TypeDef; /** * @brief Controller Area Network FilterRegister */ typedef struct { __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ } CAN_FilterRegister_TypeDef; /** * @brief Controller Area Network */ typedef struct { __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ uint32_t RESERVED2; /*!< Reserved, 0x208 */ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ uint32_t RESERVED3; /*!< Reserved, 0x210 */ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ uint32_t RESERVED4; /*!< Reserved, 0x218 */ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ } CAN_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ uint8_t RESERVED0; /*!< Reserved, 0x05 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ } CRC_TypeDef; /** * @brief Digital to Analog Converter */ typedef struct { __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ } DAC_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ }DBGMCU_TypeDef; /** * @brief DCMI */ typedef struct { __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ } DCMI_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; typedef struct { __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ } DMA_TypeDef; /** * @brief Ethernet MAC */ typedef struct { __IO uint32_t MACCR; __IO uint32_t MACFFR; __IO uint32_t MACHTHR; __IO uint32_t MACHTLR; __IO uint32_t MACMIIAR; __IO uint32_t MACMIIDR; __IO uint32_t MACFCR; __IO uint32_t MACVLANTR; /* 8 */ uint32_t RESERVED0[2]; __IO uint32_t MACRWUFFR; /* 11 */ __IO uint32_t MACPMTCSR; uint32_t RESERVED1[2]; __IO uint32_t MACSR; /* 15 */ __IO uint32_t MACIMR; __IO uint32_t MACA0HR; __IO uint32_t MACA0LR; __IO uint32_t MACA1HR; __IO uint32_t MACA1LR; __IO uint32_t MACA2HR; __IO uint32_t MACA2LR; __IO uint32_t MACA3HR; __IO uint32_t MACA3LR; /* 24 */ uint32_t RESERVED2[40]; __IO uint32_t MMCCR; /* 65 */ __IO uint32_t MMCRIR; __IO uint32_t MMCTIR; __IO uint32_t MMCRIMR; __IO uint32_t MMCTIMR; /* 69 */ uint32_t RESERVED3[14]; __IO uint32_t MMCTGFSCCR; /* 84 */ __IO uint32_t MMCTGFMSCCR; uint32_t RESERVED4[5]; __IO uint32_t MMCTGFCR; uint32_t RESERVED5[10]; __IO uint32_t MMCRFCECR; __IO uint32_t MMCRFAECR; uint32_t RESERVED6[10]; __IO uint32_t MMCRGUFCR; uint32_t RESERVED7[334]; __IO uint32_t PTPTSCR; __IO uint32_t PTPSSIR; __IO uint32_t PTPTSHR; __IO uint32_t PTPTSLR; __IO uint32_t PTPTSHUR; __IO uint32_t PTPTSLUR; __IO uint32_t PTPTSAR; __IO uint32_t PTPTTHR; __IO uint32_t PTPTTLR; __IO uint32_t RESERVED8; __IO uint32_t PTPTSSR; /* added for STM32F2xx */ uint32_t RESERVED9[565]; __IO uint32_t DMABMR; __IO uint32_t DMATPDR; __IO uint32_t DMARPDR; __IO uint32_t DMARDLAR; __IO uint32_t DMATDLAR; __IO uint32_t DMASR; __IO uint32_t DMAOMR; __IO uint32_t DMAIER; __IO uint32_t DMAMFBOCR; __IO uint32_t DMARSWTR; /* added for STM32F2xx */ uint32_t RESERVED10[8]; __IO uint32_t DMACHTDR; __IO uint32_t DMACHRDR; __IO uint32_t DMACHTBAR; __IO uint32_t DMACHRBAR; } ETH_TypeDef; /** * @brief External Interrupt/Event Controller */ typedef struct { __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ } EXTI_TypeDef; /** * @brief FLASH Registers */ typedef struct { __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */ } FLASH_TypeDef; /** * @brief Flexible Static Memory Controller */ typedef struct { __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ } FSMC_Bank1_TypeDef; /** * @brief Flexible Static Memory Controller Bank1E */ typedef struct { __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ } FSMC_Bank1E_TypeDef; /** * @brief Flexible Static Memory Controller Bank2 */ typedef struct { __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ uint32_t RESERVED0; /*!< Reserved, 0x70 */ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ } FSMC_Bank2_TypeDef; /** * @brief Flexible Static Memory Controller Bank3 */ typedef struct { __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ uint32_t RESERVED0; /*!< Reserved, 0x90 */ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ } FSMC_Bank3_TypeDef; /** * @brief Flexible Static Memory Controller Bank4 */ typedef struct { __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ } FSMC_Bank4_TypeDef; /** * @brief General Purpose I/O */ typedef struct { __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x24-0x28 */ } GPIO_TypeDef; /** * @brief System configuration controller */ typedef struct { __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ } SYSCFG_TypeDef; /** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ uint16_t RESERVED0; /*!< Reserved, 0x02 */ __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ uint16_t RESERVED2; /*!< Reserved, 0x0A */ __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ uint16_t RESERVED3; /*!< Reserved, 0x0E */ __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ uint16_t RESERVED4; /*!< Reserved, 0x12 */ __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ uint16_t RESERVED5; /*!< Reserved, 0x16 */ __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ uint16_t RESERVED6; /*!< Reserved, 0x1A */ __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ uint16_t RESERVED7; /*!< Reserved, 0x1E */ __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ uint16_t RESERVED8; /*!< Reserved, 0x22 */ } I2C_TypeDef; /** * @brief Independent WATCHDOG */ typedef struct { __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ } IWDG_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ } PWR_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ uint32_t RESERVED0; /*!< Reserved, 0x1C */ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ uint32_t RESERVED2; /*!< Reserved, 0x3C */ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ uint32_t RESERVED4; /*!< Reserved, 0x5C */ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ } RCC_TypeDef; /** * @brief Real-Time Clock */ typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ uint32_t RESERVED1; /*!< Reserved, 0x28 */ uint32_t RESERVED2; /*!< Reserved, 0x2C */ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ uint32_t RESERVED3; /*!< Reserved, 0x38 */ uint32_t RESERVED4; /*!< Reserved, 0x3C */ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ uint32_t RESERVED5; /*!< Reserved, 0x44 */ uint32_t RESERVED6; /*!< Reserved, 0x48 */ uint32_t RESERVED7; /*!< Reserved, 0x4C */ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ } RTC_TypeDef; /** * @brief SD host Interface */ typedef struct { __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ } SDIO_TypeDef; /** * @brief Serial Peripheral Interface */ typedef struct { __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ uint16_t RESERVED0; /*!< Reserved, 0x02 */ __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ uint16_t RESERVED2; /*!< Reserved, 0x0A */ __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ uint16_t RESERVED3; /*!< Reserved, 0x0E */ __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ uint16_t RESERVED4; /*!< Reserved, 0x12 */ __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ uint16_t RESERVED5; /*!< Reserved, 0x16 */ __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ uint16_t RESERVED6; /*!< Reserved, 0x1A */ __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ uint16_t RESERVED7; /*!< Reserved, 0x1E */ __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ uint16_t RESERVED8; /*!< Reserved, 0x22 */ } SPI_TypeDef; /** * @brief TIM */ typedef struct { __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ uint16_t RESERVED0; /*!< Reserved, 0x02 */ __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ uint16_t RESERVED2; /*!< Reserved, 0x0A */ __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ uint16_t RESERVED3; /*!< Reserved, 0x0E */ __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ uint16_t RESERVED4; /*!< Reserved, 0x12 */ __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ uint16_t RESERVED5; /*!< Reserved, 0x16 */ __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ uint16_t RESERVED6; /*!< Reserved, 0x1A */ __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ uint16_t RESERVED7; /*!< Reserved, 0x1E */ __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ uint16_t RESERVED8; /*!< Reserved, 0x22 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ uint16_t RESERVED9; /*!< Reserved, 0x2A */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ uint16_t RESERVED10; /*!< Reserved, 0x32 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ uint16_t RESERVED11; /*!< Reserved, 0x46 */ __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ uint16_t RESERVED12; /*!< Reserved, 0x4A */ __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ uint16_t RESERVED13; /*!< Reserved, 0x4E */ __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ uint16_t RESERVED14; /*!< Reserved, 0x52 */ } TIM_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ uint16_t RESERVED0; /*!< Reserved, 0x02 */ __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ uint16_t RESERVED2; /*!< Reserved, 0x0A */ __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ uint16_t RESERVED3; /*!< Reserved, 0x0E */ __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ uint16_t RESERVED4; /*!< Reserved, 0x12 */ __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ uint16_t RESERVED5; /*!< Reserved, 0x16 */ __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ uint16_t RESERVED6; /*!< Reserved, 0x1A */ } USART_TypeDef; /** * @brief Window WATCHDOG */ typedef struct { __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; /** * @brief Crypto Processor */ typedef struct { __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ } CRYP_TypeDef; /** * @brief HASH */ typedef struct { __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ } HASH_TypeDef; /** * @brief HASH */ typedef struct { __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ } RNG_TypeDef; /** * @brief USB OTG FS */ #pragma anon_unions typedef struct { __IO uint32_t GOTGCTL; __IO uint32_t GOTGINT; __IO uint32_t GAHBCFG; __IO uint32_t GUSBCFG; __IO uint32_t GRSTCTL; __IO uint32_t GINTSTS; __IO uint32_t GINTMSK; __IO uint32_t GRXSTSR; __IO uint32_t GRXSTSP; __IO uint32_t GRXFSIZ; union { __IO uint32_t HNPTXFSIZ; __IO uint32_t DIEPTXF0; }; __IO uint32_t HNPTXSTS; __IO uint32_t GI2CCTL; uint32_t RESERVED0; __IO uint32_t GCCFG; __IO uint32_t CID; uint32_t RESERVED1[48]; __IO uint32_t HPTXFSIZ; __IO uint32_t DIEPTXF1; __IO uint32_t DIEPTXF2; __IO uint32_t DIEPTXF3; __IO uint32_t DIEPTXF4; __IO uint32_t DIEPTXF5; __IO uint32_t DIEPTXF6; __IO uint32_t DIEPTXF7; __IO uint32_t DIEPTXF8; __IO uint32_t DIEPTXF9; __IO uint32_t DIEPTXF10; __IO uint32_t DIEPTXF11; __IO uint32_t DIEPTXF12; __IO uint32_t DIEPTXF13; __IO uint32_t DIEPTXF14; __IO uint32_t DIEPTXF15; uint32_t RESERVED2[176]; __IO uint32_t HCFG; __IO uint32_t HFIR; __IO uint32_t HFNUM; uint32_t RESERVED3; __IO uint32_t HPTXSTS; __IO uint32_t HAINT; __IO uint32_t HAINTMSK; uint32_t RESERVED4[9]; __IO uint32_t HPRT; uint32_t RESERVED5[47]; __IO uint32_t HCCHAR0; uint32_t RESERVED6; __IO uint32_t HCINT0; __IO uint32_t HCINTMSK0; __IO uint32_t HCTSIZ0; uint32_t RESERVED7[3]; __IO uint32_t HCCHAR1; uint32_t RESERVED8; __IO uint32_t HCINT1; __IO uint32_t HCINTMSK1; __IO uint32_t HCTSIZ1; uint32_t RESERVED9[3]; __IO uint32_t HCCHAR2; uint32_t RESERVED10; __IO uint32_t HCINT2; __IO uint32_t HCINTMSK2; __IO uint32_t HCTSIZ2; uint32_t RESERVED11[3]; __IO uint32_t HCCHR3; uint32_t RESERVED12; __IO uint32_t HCINT3; __IO uint32_t HCINTMSK3; __IO uint32_t HCTSIZ3; uint32_t RESERVED13[3]; __IO uint32_t HCCHR4; uint32_t RESERVED14; __IO uint32_t HCINT4; __IO uint32_t HCINTMSK4; __IO uint32_t HCTSIZ4; uint32_t RESERVED15[3]; __IO uint32_t HCCHR5; uint32_t RESERVED16; __IO uint32_t HCINT5; __IO uint32_t HCINTMSK5; __IO uint32_t HCTSIZ5; uint32_t RESERVED17[3]; __IO uint32_t HCCHR6; uint32_t RESERVED18; __IO uint32_t HCINT6; __IO uint32_t HCINTMSK6; __IO uint32_t HCTSIZ6; uint32_t RESERVED19[3]; __IO uint32_t HCCHR7; uint32_t RESERVED20; __IO uint32_t HCINT7; __IO uint32_t HCINTMSK7; __IO uint32_t HCTSIZ7; uint32_t RESERVED21[3]; __IO uint32_t HCCHR8; uint32_t RESERVED22; __IO uint32_t HCINT8; __IO uint32_t HCINTMSK8; __IO uint32_t HCTSIZ8; uint32_t RESERVED23[3]; __IO uint32_t HCCHR9; uint32_t RESERVED24; __IO uint32_t HCINT9; __IO uint32_t HCINTMSK9; __IO uint32_t HCTSIZ9; uint32_t RESERVED25[3]; __IO uint32_t HCCHR10; uint32_t RESERVED26; __IO uint32_t HCINT10; __IO uint32_t HCINTMSK10; __IO uint32_t HCTSIZ10; uint32_t RESERVED27[3]; __IO uint32_t HCCHR11; uint32_t RESERVED28; __IO uint32_t HCINT11; __IO uint32_t HCINTMSK11; __IO uint32_t HCTSIZ11; uint32_t RESERVED29[3]; __IO uint32_t HCCHR12; uint32_t RESERVED30; __IO uint32_t HCINT12; __IO uint32_t HCINTMSK12; __IO uint32_t HCTSIZ12; uint32_t RESERVED31[3]; __IO uint32_t HCCHR13; uint32_t RESERVED32; __IO uint32_t HCINT13; __IO uint32_t HCINTMSK13; __IO uint32_t HCTSIZ13; uint32_t RESERVED33[3]; __IO uint32_t HCCHR14; uint32_t RESERVED34; __IO uint32_t HCINT14; __IO uint32_t HCINTMSK14; __IO uint32_t HCTSIZ14; uint32_t RESERVED35[3]; __IO uint32_t HCCHR15; uint32_t RESERVED36; __IO uint32_t HCINT15; __IO uint32_t HCINTMSK15; __IO uint32_t HCTSIZ15; uint32_t RESERVED37[3]; uint32_t RESERVED38[64]; __IO uint32_t DCFG; __IO uint32_t DCTL; __IO uint32_t DSTS; uint32_t RESERVED39; __IO uint32_t DIEPMSK; __IO uint32_t DOEPMSK; __IO uint32_t DAINT; __IO uint32_t DAINTMSK; uint32_t RESERVED40[2]; __IO uint32_t DVBUSDIS; __IO uint32_t DVBUSPULSE; uint32_t RESERVED41; __IO uint32_t DIEPEMPMSK; uint32_t RESERVED42[50]; __IO uint32_t DIEPCTL0; uint32_t RESERVED43; __IO uint32_t DIEPINT0; uint32_t RESERVED44; __IO uint32_t DIEPTSIZ0; uint32_t RESERVED45; __IO uint32_t DTXFSTS0; uint32_t RESERVED46; __IO uint32_t DIEPCTL1; uint32_t RESERVED47; __IO uint32_t DIEPINT1; uint32_t RESERVED48; __IO uint32_t DIEPTSIZ1; uint32_t RESERVED49; __IO uint32_t DTXFSTS1; uint32_t RESERVED50; __IO uint32_t DIEPCTL2; uint32_t RESERVED51; __IO uint32_t DIEPINT2; uint32_t RESERVED52; __IO uint32_t DIEPTSIZ2; uint32_t RESERVED53; __IO uint32_t DTXFSTS2; uint32_t RESERVED54; __IO uint32_t DIEPCTL3; uint32_t RESERVED55; __IO uint32_t DIEPINT3; uint32_t RESERVED56; __IO uint32_t DIEPTSIZ3; uint32_t RESERVED57; __IO uint32_t DTXFSTS3; uint32_t RESERVED58; __IO uint32_t DIEPCTL4; uint32_t RESERVED59; __IO uint32_t DIEPINT4; uint32_t RESERVED60; __IO uint32_t DIEPTSIZ4; uint32_t RESERVED61; __IO uint32_t DTXFSTS4; uint32_t RESERVED62; __IO uint32_t DIEPCTL5; uint32_t RESERVED63; __IO uint32_t DIEPINT5; uint32_t RESERVED64; __IO uint32_t DIEPTSIZ5; uint32_t RESERVED65[3]; __IO uint32_t DIEPCTL6; uint32_t RESERVED66; __IO uint32_t DIEPINT6; uint32_t RESERVED67; __IO uint32_t DIEPTSIZ6; uint32_t RESERVED68[3]; __IO uint32_t DIEPCTL7; uint32_t RESERVED69; __IO uint32_t DIEPINT7; uint32_t RESERVED70; __IO uint32_t DIEPTSIZ7; uint32_t RESERVED71[3]; __IO uint32_t DIEPCTL8; uint32_t RESERVED72; __IO uint32_t DIEPINT8; uint32_t RESERVED73; __IO uint32_t DIEPTSIZ8; uint32_t RESERVED74[3]; __IO uint32_t DIEPCTL9; uint32_t RESERVED75; __IO uint32_t DIEPINT9; uint32_t RESERVED76; __IO uint32_t DIEPTSIZ9; uint32_t RESERVED77[3]; __IO uint32_t DIEPCTL10; uint32_t RESERVED78; __IO uint32_t DIEPINT10; uint32_t RESERVED79; __IO uint32_t DIEPTSIZ10; uint32_t RESERVED80[3]; __IO uint32_t DIEPCTL11; uint32_t RESERVED81; __IO uint32_t DIEPINT11; uint32_t RESERVED82; __IO uint32_t DIEPTSIZ11; uint32_t RESERVED83[3]; __IO uint32_t DIEPCTL12; uint32_t RESERVED84; __IO uint32_t DIEPINT12; uint32_t RESERVED85; __IO uint32_t DIEPTSIZ86; uint32_t RESERVED86[3]; __IO uint32_t DIEPCTL13; uint32_t RESERVED87; __IO uint32_t DIEPINT13; uint32_t RESERVED88; __IO uint32_t DIEPTSIZ13; uint32_t RESERVED89[3]; __IO uint32_t DIEPCTL14; uint32_t RESERVED90; __IO uint32_t DIEPINT14; uint32_t RESERVED91; __IO uint32_t DIEPTSIZ14; uint32_t RESERVED92[3]; __IO uint32_t DIEPCTL15; uint32_t RESERVED93; __IO uint32_t DIEPINT15; uint32_t RESERVED94; __IO uint32_t DIEPTSIZ15; uint32_t RESERVED95[3]; __IO uint32_t DOEPCTL0; uint32_t RESERVED96; __IO uint32_t DOEPINT0; uint32_t RESERVED97; __IO uint32_t DOEPTSIZ0; uint32_t RESERVED98[3]; __IO uint32_t DOEPCTL1; uint32_t RESERVED99; __IO uint32_t DOEPINT1; uint32_t RESERVED100; __IO uint32_t DOEPTSIZ1; uint32_t RESERVED101[3]; __IO uint32_t DOEPCTL2; uint32_t RESERVED102; __IO uint32_t DOEPINT2; uint32_t RESERVED103; __IO uint32_t DOEPTSIZ2; uint32_t RESERVED104[3]; __IO uint32_t DOEPCTL3; uint32_t RESERVED105; __IO uint32_t DOEPINT3; uint32_t RESERVED106; __IO uint32_t DOEPTSIZ3; uint32_t RESERVED107[3]; __IO uint32_t DOEPCTL4; uint32_t RESERVED108; __IO uint32_t DOEPINT4; uint32_t RESERVED109; __IO uint32_t DOEPTSIZ4; uint32_t RESERVED110[3]; __IO uint32_t DOEPCTL5; uint32_t RESERVED111; __IO uint32_t DOEPINT5; uint32_t RESERVED112; __IO uint32_t DOEPTSIZ5; uint32_t RESERVED113[3]; __IO uint32_t DOEPCTL6; uint32_t RESERVED114; __IO uint32_t DOEPINT6; uint32_t RESERVED115; __IO uint32_t DOEPTSIZ6; uint32_t RESERVED116[3]; __IO uint32_t DOEPCTL7; uint32_t RESERVED117; __IO uint32_t DOEPINT7; uint32_t RESERVED118; __IO uint32_t DOEPTSIZ7; uint32_t RESERVED119[3]; __IO uint32_t DOEPCTL8; uint32_t RESERVED120; __IO uint32_t DOEPINT8; uint32_t RESERVED121; __IO uint32_t DOEPTSIZ8; uint32_t RESERVED122[3]; __IO uint32_t DOEPCTL9; uint32_t RESERVED123; __IO uint32_t DOEPINT9; uint32_t RESERVED124; __IO uint32_t DOEPTSIZ9; uint32_t RESERVED125[3]; __IO uint32_t DOEPCTL10; uint32_t RESERVED126; __IO uint32_t DOEPINT10; uint32_t RESERVED127; __IO uint32_t DOEPTSIZ10; uint32_t RESERVED128[3]; __IO uint32_t DOEPCTL11; uint32_t RESERVED129; __IO uint32_t DOEPINT11; uint32_t RESERVED130; __IO uint32_t DOEPTSIZ11; uint32_t RESERVED131[3]; __IO uint32_t DOEPCTL12; uint32_t RESERVED132; __IO uint32_t DOEPINT12; uint32_t RESERVED133; __IO uint32_t DOEPTSIZ12; uint32_t RESERVED134[3]; __IO uint32_t DOEPCTL13; uint32_t RESERVED135; __IO uint32_t DOEPINT13; uint32_t RESERVED136; __IO uint32_t DOEPTSIZ13; uint32_t RESERVED137[3]; __IO uint32_t DOEPCTL14; uint32_t RESERVED138; __IO uint32_t DOEPINT14; uint32_t RESERVED139; __IO uint32_t DOEPTSIZ14; uint32_t RESERVED140[3]; __IO uint32_t DOEPCTL15; uint32_t RESERVED141; __IO uint32_t DOEPINT15; uint32_t RESERVED142; __IO uint32_t DOEPTSIZ15; uint32_t RESERVED143[3]; uint32_t RESERVED144[64]; __IO uint32_t PCGCCTL; } OTG_FS_TypeDef; /** * @brief USB OTG HS */ typedef struct { __IO uint32_t GOTGCTL; __IO uint32_t GOTGINT; __IO uint32_t GAHBCFG; __IO uint32_t GUSBCFG; __IO uint32_t GRSTCTL; __IO uint32_t GINTSTS; __IO uint32_t GINTMSK; __IO uint32_t GRXSTSR; __IO uint32_t GRXSTSP; __IO uint32_t GRXFSIZ; union { __IO uint32_t GNPTXFSIZ; __IO uint32_t TX0FSIZ; }; __IO uint32_t GNPTXSTS; __IO uint32_t GI2CCTL; uint32_t RESERVED0; __IO uint32_t GCCFG; __IO uint32_t CID; uint32_t RESERVED1[48]; __IO uint32_t HPTXFSIZ; __IO uint32_t DIEPTXF1; __IO uint32_t DIEPTXF2; __IO uint32_t DIEPTXF3; __IO uint32_t DIEPTXF4; __IO uint32_t DIEPTXF5; __IO uint32_t DIEPTXF6; __IO uint32_t DIEPTXF7; __IO uint32_t DIEPTXF8; __IO uint32_t DIEPTXF9; __IO uint32_t DIEPTXF10; __IO uint32_t DIEPTXF11; __IO uint32_t DIEPTXF12; __IO uint32_t DIEPTXF13; __IO uint32_t DIEPTXF14; __IO uint32_t DIEPTXF15; uint32_t RESERVED2[176]; __IO uint32_t HCFG; __IO uint32_t HFIR; __IO uint32_t HFNUM; uint32_t RESERVED3; __IO uint32_t HPTXSTS; __IO uint32_t HAINT; __IO uint32_t HAINTMSK; uint32_t RESERVED4[9]; __IO uint32_t HPRT; uint32_t RESERVED5[47]; __IO uint32_t HCCHAR0; __IO uint32_t HCSPLT0; __IO uint32_t HCINT0; __IO uint32_t HCINTMSK0; __IO uint32_t HCTSIZ0; __IO uint32_t HCDMA0; uint32_t RESERVED6[2]; __IO uint32_t HCCHAR1; __IO uint32_t HCSPLT1; __IO uint32_t HCINT1; __IO uint32_t HCINTMSK1; __IO uint32_t HCTSIZ1; __IO uint32_t HCDMA1; uint32_t RESERVED7[2]; __IO uint32_t HCCHAR2; __IO uint32_t HCSPLT2; __IO uint32_t HCINT2; __IO uint32_t HCINTMSK2; __IO uint32_t HCTSIZ2; __IO uint32_t HCDMA2; uint32_t RESERVED8[2]; __IO uint32_t HCCHAR3; __IO uint32_t HCSPLT3; __IO uint32_t HCINT3; __IO uint32_t HCINTMSK3; __IO uint32_t HCTSIZ3; __IO uint32_t HCDMA3; uint32_t RESERVED9[2]; __IO uint32_t HCCHAR4; __IO uint32_t HCSPLT4; __IO uint32_t HCINT4; __IO uint32_t HCINTMSK4; __IO uint32_t HCTSIZ4; __IO uint32_t HCDMA4; uint32_t RESERVED10[2]; __IO uint32_t HCCHAR5; __IO uint32_t HCSPLT5; __IO uint32_t HCINT5; __IO uint32_t HCINTMSK5; __IO uint32_t HCTSIZ5; __IO uint32_t HCDMA5; uint32_t RESERVED11[2]; __IO uint32_t HCCHAR6; __IO uint32_t HCSPLT6; __IO uint32_t HCINT6; __IO uint32_t HCINTMSK6; __IO uint32_t HCTSIZ6; __IO uint32_t HCDMA6; uint32_t RESERVED12[2]; __IO uint32_t HCCHAR7; __IO uint32_t HCSPLT7; __IO uint32_t HCINT7; __IO uint32_t HCINTMSK7; __IO uint32_t HCTSIZ7; __IO uint32_t HCDMA7; uint32_t RESERVED13[2]; __IO uint32_t HCCHAR8; __IO uint32_t HCSPLT8; __IO uint32_t HCINT8; __IO uint32_t HCINTMSK8; __IO uint32_t HCTSIZ8; __IO uint32_t HCDMA8; uint32_t RESERVED14[2]; __IO uint32_t HCCHAR9; __IO uint32_t HCSPLT9; __IO uint32_t HCINT9; __IO uint32_t HCINTMSK9; __IO uint32_t HCTSIZ9; __IO uint32_t HCDMA9; uint32_t RESERVED15[2]; __IO uint32_t HCCHAR10; __IO uint32_t HCSPLT10; __IO uint32_t HCINT10; __IO uint32_t HCINTMSK10; __IO uint32_t HCTSIZ10; __IO uint32_t HCDMA10; uint32_t RESERVED16[2]; __IO uint32_t HCCHAR11; __IO uint32_t HCSPLT11; __IO uint32_t HCINT11; __IO uint32_t HCINTMSK11; __IO uint32_t HCTSIZ11; __IO uint32_t HCDMA11; uint32_t RESERVED17[2]; __IO uint32_t HCCHAR12; __IO uint32_t HCSPLT12; __IO uint32_t HCINT12; __IO uint32_t HCINTMSK12; __IO uint32_t HCTSIZ12; __IO uint32_t HCDMA12; uint32_t RESERVED18[2]; __IO uint32_t HCCHAR13; __IO uint32_t HCSPLT13; __IO uint32_t HCINT13; __IO uint32_t HCINTMSK13; __IO uint32_t HCTSIZ13; __IO uint32_t HCDMA13; uint32_t RESERVED19[2]; __IO uint32_t HCCHAR14; __IO uint32_t HCSPLT14; __IO uint32_t HCINT14; __IO uint32_t HCINTMSK14; __IO uint32_t HCTSIZ14; __IO uint32_t HCDMA14; uint32_t RESERVED20[2]; __IO uint32_t HCCHAR15; __IO uint32_t HCSPLT15; __IO uint32_t HCINT15; __IO uint32_t HCINTMSK15; __IO uint32_t HCTSIZ15; __IO uint32_t HCDMA15; uint32_t RESERVED21[2]; uint32_t RESERVED22[64]; __IO uint32_t DCFG; __IO uint32_t DCTL; __IO uint32_t DSTS; uint32_t RESERVED23; __IO uint32_t DIEPMSK; __IO uint32_t DOEPMSK; __IO uint32_t DAINT; __IO uint32_t DAINTMSK; uint32_t RESERVED24[2]; __IO uint32_t DVBUSDIS; __IO uint32_t DVBUSPULSE; uint32_t RESERVED25; __IO uint32_t DIEPEMPMSK; __IO uint32_t EACHHINT; __IO uint32_t EACHHINTMSK; __IO uint32_t DIEPEACHMSK1; uint32_t RESERVED26[15]; __IO uint32_t DOEPEACHMSK1; uint32_t RESERVED27[31]; __IO uint32_t DIEPCTL0; uint32_t RESERVED28; __IO uint32_t DIEPINT0; uint32_t RESERVED29; __IO uint32_t DIEPTSIZ0; __IO uint32_t DIEPDMA0; __IO uint32_t DTXFSTS0; uint32_t RESERVED30; __IO uint32_t DIEPCTL1; uint32_t RESERVED31; __IO uint32_t DIEPINT1; uint32_t RESERVED32; __IO uint32_t DIEPTSIZ1; __IO uint32_t DIEPDMA1; __IO uint32_t DTXFSTS1; uint32_t RESERVED33; __IO uint32_t DIEPCTL2; uint32_t RESERVED34; __IO uint32_t DIEPINT2; uint32_t RESERVED35; __IO uint32_t DIEPTSIZ2; __IO uint32_t DIEPDMA2; __IO uint32_t DTXFSTS2; uint32_t RESERVED36; __IO uint32_t DIEPCTL3; uint32_t RESERVED37; __IO uint32_t DIEPINT3; uint32_t RESERVED38; __IO uint32_t DIEPTSIZ3; __IO uint32_t DIEPDMA3; __IO uint32_t DTXFSTS3; uint32_t RESERVED39; __IO uint32_t DIEPCTL4; uint32_t RESERVED40; __IO uint32_t DIEPINT4; uint32_t RESERVED41; __IO uint32_t DIEPTSIZ4; __IO uint32_t DIEPDMA4; __IO uint32_t DTXFSTS4; uint32_t RESERVED42; __IO uint32_t DIEPCTL5; uint32_t RESERVED43; __IO uint32_t DIEPINT5; uint32_t RESERVED44; __IO uint32_t DIEPTSIZ5; __IO uint32_t DIEPDMA5; __IO uint32_t DTXFSTS5; uint32_t RESERVED45; __IO uint32_t DIEPCTL6; uint32_t RESERVED46; __IO uint32_t DIEPINT6; uint32_t RESERVED47; __IO uint32_t DIEPTSIZ6; __IO uint32_t DIEPDMA6; __IO uint32_t DTXFSTS6; uint32_t RESERVED48; __IO uint32_t DIEPCTL7; uint32_t RESERVED49; __IO uint32_t DIEPINT7; uint32_t RESERVED50; __IO uint32_t DIEPTSIZ7; __IO uint32_t DIEPDMA7; __IO uint32_t DTXFSTS7; uint32_t RESERVED51; __IO uint32_t DIEPCTL8; uint32_t RESERVED52; __IO uint32_t DIEPINT8; uint32_t RESERVED53; __IO uint32_t DIEPTSIZ8; __IO uint32_t DIEPDMA8; __IO uint32_t DTXFSTS8; uint32_t RESERVED54; __IO uint32_t DIEPCTL9; uint32_t RESERVED55; __IO uint32_t DIEPINT9; uint32_t RESERVED56; __IO uint32_t DIEPTSIZ9; __IO uint32_t DIEPDMA9; __IO uint32_t DTXFSTS9; uint32_t RESERVED57; __IO uint32_t DIEPCTL10; uint32_t RESERVED58; __IO uint32_t DIEPINT10; uint32_t RESERVED59; __IO uint32_t DIEPTSIZ10; __IO uint32_t DIEPDMA10; __IO uint32_t DTXFSTS10; uint32_t RESERVED60; __IO uint32_t DIEPCTL11; uint32_t RESERVED61; __IO uint32_t DIEPINT11; uint32_t RESERVED62; __IO uint32_t DIEPTSIZ11; __IO uint32_t DIEPDMA11; __IO uint32_t DTXFSTS11; uint32_t RESERVED63; __IO uint32_t DIEPCTL12; uint32_t RESERVED64; __IO uint32_t DIEPINT12; uint32_t RESERVED65; __IO uint32_t DIEPTSIZ12; __IO uint32_t DIEPDMA12; __IO uint32_t DTXFSTS12; uint32_t RESERVED66; __IO uint32_t DIEPCTL13; uint32_t RESERVED67; __IO uint32_t DIEPINT13; uint32_t RESERVED68; __IO uint32_t DIEPTSIZ13; __IO uint32_t DIEPDMA13; __IO uint32_t DTXFSTS13; uint32_t RESERVED69; __IO uint32_t DIEPCTL14; uint32_t RESERVED70; __IO uint32_t DIEPINT14; uint32_t RESERVED71; __IO uint32_t DIEPTSIZ14; __IO uint32_t DIEPDMA14; __IO uint32_t DTXFSTS14; uint32_t RESERVED72; __IO uint32_t DIEPCTL15; uint32_t RESERVED73; __IO uint32_t DIEPINT15; uint32_t RESERVED74; __IO uint32_t DIEPTSIZ15; __IO uint32_t DIEPDMA15; __IO uint32_t DTXFSTS15; uint32_t RESERVED75; __IO uint32_t DOEPCTL0; uint32_t RESERVED76; __IO uint32_t DOEPINT0; uint32_t RESERVED77; __IO uint32_t DOEPTSIZ0; __IO uint32_t DOEPDMAB0; uint32_t RESERVED78[2]; __IO uint32_t DOEPCTL1; uint32_t RESERVED79; __IO uint32_t DOEPINT1; uint32_t RESERVED80; __IO uint32_t DOEPTSIZ1; __IO uint32_t DOEPDMAB1; uint32_t RESERVED81[2]; __IO uint32_t DOEPCTL2; uint32_t RESERVED82; __IO uint32_t DOEPINT2; uint32_t RESERVED83; __IO uint32_t DOEPTSIZ2; __IO uint32_t DOEPDMAB2; uint32_t RESERVED84[2]; __IO uint32_t DOEPCTL3; uint32_t RESERVED85; __IO uint32_t DOEPINT3; uint32_t RESERVED86; __IO uint32_t DOEPTSIZ3; __IO uint32_t DOEPDMAB3; uint32_t RESERVED87[2]; __IO uint32_t DOEPCTL4; uint32_t RESERVED88; __IO uint32_t DOEPINT4; uint32_t RESERVED89; __IO uint32_t DOEPTSIZ4; __IO uint32_t DOEPDMAB4; uint32_t RESERVED90[2]; __IO uint32_t DOEPCTL5; uint32_t RESERVED91; __IO uint32_t DOEPINT5; uint32_t RESERVED92; __IO uint32_t DOEPTSIZ5; __IO uint32_t DOEPDMAB5; uint32_t RESERVED93[2]; __IO uint32_t DOEPCTL6; uint32_t RESERVED94; __IO uint32_t DOEPINT6; uint32_t RESERVED95; __IO uint32_t DOEPTSIZ6; __IO uint32_t DOEPDMAB6; uint32_t RESERVED96[2]; __IO uint32_t DOEPCTL7; uint32_t RESERVED97; __IO uint32_t DOEPINT7; uint32_t RESERVED98; __IO uint32_t DOEPTSIZ7; __IO uint32_t DOEPDMAB7; uint32_t RESERVED99[2]; __IO uint32_t DOEPCTL8; uint32_t RESERVED100; __IO uint32_t DOEPINT8; uint32_t RESERVED101; __IO uint32_t DOEPTSIZ8; __IO uint32_t DOEPDMAB8; uint32_t RESERVED102[2]; __IO uint32_t DOEPCTL9; uint32_t RESERVED103; __IO uint32_t DOEPINT9; uint32_t RESERVED104; __IO uint32_t DOEPTSIZ9; __IO uint32_t DOEPDMAB9; uint32_t RESERVED105[2]; __IO uint32_t DOEPCTL10; uint32_t RESERVED106; __IO uint32_t DOEPINT10; uint32_t RESERVED107; __IO uint32_t DOEPTSIZ10; __IO uint32_t DOEPDMAB10; uint32_t RESERVED108[2]; __IO uint32_t DOEPCTL11; uint32_t RESERVED109; __IO uint32_t DOEPINT11; uint32_t RESERVED110; __IO uint32_t DOEPTSIZ11; __IO uint32_t DOEPDMAB11; uint32_t RESERVED111[2]; __IO uint32_t DOEPCTL12; uint32_t RESERVED112; __IO uint32_t DOEPINT12; uint32_t RESERVED113; __IO uint32_t DOEPTSIZ12; __IO uint32_t DOEPDMAB12; uint32_t RESERVED114[2]; __IO uint32_t DOEPCTL13; uint32_t RESERVED115; __IO uint32_t DOEPINT13; uint32_t RESERVED116; __IO uint32_t DOEPTSIZ13; __IO uint32_t DOEPDMAB13; uint32_t RESERVED117[2]; __IO uint32_t DOEPCTL14; uint32_t RESERVED118; __IO uint32_t DOEPINT14; uint32_t RESERVED119; __IO uint32_t DOEPTSIZ14; __IO uint32_t DOEPDMAB14; uint32_t RESERVED120[2]; __IO uint32_t DOEPCTL15; uint32_t RESERVED121; __IO uint32_t DOEPINT15; uint32_t RESERVED122; __IO uint32_t DOEPTSIZ15; __IO uint32_t DOEPDMAB15; uint32_t RESERVED123[2]; uint32_t RESERVED143[64]; __IO uint32_t PCGCCTL; } OTG_HS_TypeDef; #pragma no_anon_unions /** * @} */ /** @addtogroup Peripheral_memory_map * @{ */ #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) /*!< APB1 peripherals */ #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) #define TIM12_BASE (APB1PERIPH_BASE + 0x1800) #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) #define TIM14_BASE (APB1PERIPH_BASE + 0x2000) #define RTC_BASE (APB1PERIPH_BASE + 0x2800) #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) #define USART2_BASE (APB1PERIPH_BASE + 0x4400) #define USART3_BASE (APB1PERIPH_BASE + 0x4800) #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) #define UART5_BASE (APB1PERIPH_BASE + 0x5000) #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) #define CAN2_BASE (APB1PERIPH_BASE + 0x6800) #define PWR_BASE (APB1PERIPH_BASE + 0x7000) #define DAC_BASE (APB1PERIPH_BASE + 0x7400) /*!< APB2 peripherals */ #define TIM1_BASE (APB2PERIPH_BASE + 0x0000) #define TIM8_BASE (APB2PERIPH_BASE + 0x0400) #define USART1_BASE (APB2PERIPH_BASE + 0x1000) #define USART6_BASE (APB2PERIPH_BASE + 0x1400) #define ADC1_BASE (APB2PERIPH_BASE + 0x2000) #define ADC2_BASE (APB2PERIPH_BASE + 0x2100) #define ADC3_BASE (APB2PERIPH_BASE + 0x2200) #define ADC_BASE (APB2PERIPH_BASE + 0x2300) #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) #define TIM9_BASE (APB2PERIPH_BASE + 0x4000) #define TIM10_BASE (APB2PERIPH_BASE + 0x4400) #define TIM11_BASE (APB2PERIPH_BASE + 0x4800) /*!< AHB1 peripherals */ #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) #define CRC_BASE (AHB1PERIPH_BASE + 0x3000) #define RCC_BASE (AHB1PERIPH_BASE + 0x3800) #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) #define BKPSRAM_BASE (AHB1PERIPH_BASE + 0x4000) #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) #define DMA1_Stream0_BASE (DMA1_BASE + 0x010) #define DMA1_Stream1_BASE (DMA1_BASE + 0x028) #define DMA1_Stream2_BASE (DMA1_BASE + 0x040) #define DMA1_Stream3_BASE (DMA1_BASE + 0x058) #define DMA1_Stream4_BASE (DMA1_BASE + 0x070) #define DMA1_Stream5_BASE (DMA1_BASE + 0x088) #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) #define DMA2_Stream0_BASE (DMA2_BASE + 0x010) #define DMA2_Stream1_BASE (DMA2_BASE + 0x028) #define DMA2_Stream2_BASE (DMA2_BASE + 0x040) #define DMA2_Stream3_BASE (DMA2_BASE + 0x058) #define DMA2_Stream4_BASE (DMA2_BASE + 0x070) #define DMA2_Stream5_BASE (DMA2_BASE + 0x088) #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) #define ETH_BASE (AHB1PERIPH_BASE + 0x8000) #define ETH_MAC_BASE (ETH_BASE) #define ETH_MMC_BASE (ETH_BASE + 0x0100) #define ETH_PTP_BASE (ETH_BASE + 0x0700) #define ETH_DMA_BASE (ETH_BASE + 0x1000) #define OTG_HS_BASE (AHB1PERIPH_BASE + 0x20000) #define OTG_HS_DFIFO0_BASE (OTG_HS_BASE + 0x01000) #define OTG_HS_DFIFO1_BASE (OTG_HS_BASE + 0x02000) #define OTG_HS_DFIFO2_BASE (OTG_HS_BASE + 0x03000) #define OTG_HS_DFIFO3_BASE (OTG_HS_BASE + 0x04000) #define OTG_HS_DFIFO4_BASE (OTG_HS_BASE + 0x05000) #define OTG_HS_DFIFO5_BASE (OTG_HS_BASE + 0x06000) #define OTG_HS_DFIFO6_BASE (OTG_HS_BASE + 0x07000) #define OTG_HS_DFIFO7_BASE (OTG_HS_BASE + 0x08000) #define OTG_HS_DFIFO8_BASE (OTG_HS_BASE + 0x09000) #define OTG_HS_DFIFO9_BASE (OTG_HS_BASE + 0x0A000) #define OTG_HS_DFIFO10_BASE (OTG_HS_BASE + 0x0B000) #define OTG_HS_DFIFO11_BASE (OTG_HS_BASE + 0x0C000) #define OTG_HS_DFIFO12_BASE (OTG_HS_BASE + 0x0D000) #define OTG_HS_DFIFO13_BASE (OTG_HS_BASE + 0x0E000) #define OTG_HS_DFIFO14_BASE (OTG_HS_BASE + 0x0F000) #define OTG_HS_DFIFO15_BASE (OTG_HS_BASE + 0x10000) /*!< AHB2 peripherals */ #define OTG_FS_BASE (AHB2PERIPH_BASE + 0x00000) #define OTG_FS_DFIFO0_BASE (OTG_FS_BASE + 0x01000) #define OTG_FS_DFIFO1_BASE (OTG_FS_BASE + 0x02000) #define OTG_FS_DFIFO2_BASE (OTG_FS_BASE + 0x03000) #define OTG_FS_DFIFO3_BASE (OTG_FS_BASE + 0x04000) #define OTG_FS_DFIFO4_BASE (OTG_FS_BASE + 0x05000) #define OTG_FS_DFIFO5_BASE (OTG_FS_BASE + 0x06000) #define OTG_FS_DFIFO6_BASE (OTG_FS_BASE + 0x07000) #define OTG_FS_DFIFO7_BASE (OTG_FS_BASE + 0x08000) #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) #define HASH_BASE (AHB2PERIPH_BASE + 0x60400) #define RNG_BASE (AHB2PERIPH_BASE + 0x60800) /*!< FSMC Bankx registers base address */ #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /* Debug MCU registers base address */ #define DBGMCU_BASE ((uint32_t )0xE0042000) /** * @} */ /** @addtogroup Peripheral_declaration * @{ */ #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) #define TIM5 ((TIM_TypeDef *) TIM5_BASE) #define TIM6 ((TIM_TypeDef *) TIM6_BASE) #define TIM7 ((TIM_TypeDef *) TIM7_BASE) #define TIM12 ((TIM_TypeDef *) TIM12_BASE) #define TIM13 ((TIM_TypeDef *) TIM13_BASE) #define TIM14 ((TIM_TypeDef *) TIM14_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define WWDG ((WWDG_TypeDef *) WWDG_BASE) #define IWDG ((IWDG_TypeDef *) IWDG_BASE) #define SPI2 ((SPI_TypeDef *) SPI2_BASE) #define SPI3 ((SPI_TypeDef *) SPI3_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) #define USART3 ((USART_TypeDef *) USART3_BASE) #define UART4 ((USART_TypeDef *) UART4_BASE) #define UART5 ((USART_TypeDef *) UART5_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define CAN2 ((CAN_TypeDef *) CAN2_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define DAC ((DAC_TypeDef *) DAC_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define TIM8 ((TIM_TypeDef *) TIM8_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define USART6 ((USART_TypeDef *) USART6_BASE) #define ADC ((ADC_Common_TypeDef *) ADC_BASE) #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC2 ((ADC_TypeDef *) ADC2_BASE) #define ADC3 ((ADC_TypeDef *) ADC3_BASE) #define SDIO ((SDIO_TypeDef *) SDIO_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define TIM9 ((TIM_TypeDef *) TIM9_BASE) #define TIM10 ((TIM_TypeDef *) TIM10_BASE) #define TIM11 ((TIM_TypeDef *) TIM11_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) #define ETH ((ETH_TypeDef *) ETH_BASE) #define OTG_HS ((OTG_HS_TypeDef *) OTG_HS_BASE) #define OTG_HS_DFIFO0 (((uint32_t *) OTG_HS_DFIFO0_BASE) ) #define OTG_HS_DFIFO1 (((uint32_t *) OTG_HS_DFIFO1_BASE) ) #define OTG_HS_DFIFO2 (((uint32_t *) OTG_HS_DFIFO2_BASE) ) #define OTG_HS_DFIFO3 (((uint32_t *) OTG_HS_DFIFO3_BASE) ) #define OTG_HS_DFIFO4 (((uint32_t *) OTG_HS_DFIFO4_BASE) ) #define OTG_HS_DFIFO5 (((uint32_t *) OTG_HS_DFIFO5_BASE) ) #define OTG_HS_DFIFO6 (((uint32_t *) OTG_HS_DFIFO6_BASE) ) #define OTG_HS_DFIFO7 (((uint32_t *) OTG_HS_DFIFO7_BASE) ) #define OTG_HS_DFIFO8 (((uint32_t *) OTG_HS_DFIFO8_BASE) ) #define OTG_HS_DFIFO9 (((uint32_t *) OTG_HS_DFIFO9_BASE) ) #define OTG_HS_DFIFO10 (((uint32_t *) OTG_HS_DFIFO10_BASE) ) #define OTG_HS_DFIFO11 (((uint32_t *) OTG_HS_DFIFO11_BASE) ) #define OTG_HS_DFIFO12 (((uint32_t *) OTG_HS_DFIFO12_BASE) ) #define OTG_HS_DFIFO13 (((uint32_t *) OTG_HS_DFIFO13_BASE) ) #define OTG_HS_DFIFO14 (((uint32_t *) OTG_HS_DFIFO14_BASE) ) #define OTG_HS_DFIFO15 (((uint32_t *) OTG_HS_DFIFO15_BASE) ) #define OTG_FS ((OTG_FS_TypeDef *) OTG_FS_BASE) #define OTG_FS_DFIFO0 (((uint32_t *) OTG_FS_DFIFO0_BASE) ) #define OTG_FS_DFIFO1 (((uint32_t *) OTG_FS_DFIFO1_BASE) ) #define OTG_FS_DFIFO2 (((uint32_t *) OTG_FS_DFIFO2_BASE) ) #define OTG_FS_DFIFO3 (((uint32_t *) OTG_FS_DFIFO3_BASE) ) #define OTG_FS_DFIFO4 (((uint32_t *) OTG_FS_DFIFO4_BASE) ) #define OTG_FS_DFIFO5 (((uint32_t *) OTG_FS_DFIFO5_BASE) ) #define OTG_FS_DFIFO6 (((uint32_t *) OTG_FS_DFIFO6_BASE) ) #define OTG_FS_DFIFO7 (((uint32_t *) OTG_FS_DFIFO7_BASE) ) #define DCMI ((DCMI_TypeDef *) DCMI_BASE) #define CRYP ((CRYP_TypeDef *) CRYP_BASE) #define HASH ((HASH_TypeDef *) HASH_BASE) #define RNG ((RNG_TypeDef *) RNG_BASE) #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) /** * @} */ /** @addtogroup Exported_constants * @{ */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ /******************************************************************************/ /******************************************************************************/ /* */ /* Analog to Digital Converter */ /* */ /******************************************************************************/ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD ((uint8_t)0x01) /*!