/* ** ################################################################### ** Compilers: ARM Compiler ** Freescale C/C++ for Embedded ARM ** GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** ** Reference manual: K60P144M150SF3RM, Rev. 1, Oct 2011 ** Version: rev. 1.1, 2011-11-03 ** ** Abstract: ** CMSIS Peripheral Access Layer for MK60F15 ** ** Copyright: 1997 - 2011 Freescale Semiconductor, Inc. All Rights Reserved. ** ** http: www.freescale.com ** mail: support@freescale.com ** ** Revisions: ** - rev. 1.0 (2011-08-24) ** Initial version ** - rev. 1.1 (2011-11-03) ** Registers updated according to the new reference manual revision - Rev. 1, Oct 2011 ** Registers of the following modules have been updated - AXBS, CAN, I2S, MCG, MPU, NFC, RCM, RTC, SDHC, SIM, USBHS, WDOG ** The following modules have been removed - DDR, DRY ** ** ################################################################### */ /** * @file MK60F15.h * @version 1.1 * @date 2011-11-03 * @brief CMSIS Peripheral Access Layer for MK60F15 * * CMSIS Peripheral Access Layer for MK60F15 */ #if !defined(MK60F15_H_) #define MK60F15_H_ /**< Symbol preventing repeated inclusion */ /** Memory map major version (memory maps with equal major version number are * compatible) */ #define MCU_MEM_MAP_VERSION 0x0100u /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0001u /** * @brief Macro to access a single bit of a peripheral register (bit band region * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. * @param Reg Register to access. * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ #define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))))) /* ---------------------------------------------------------------------------- -- Interrupt vector numbers ---------------------------------------------------------------------------- */ /** * @addtogroup Interrupt_vector_numbers Interrupt vector numbers * @{ */ /** Interrupt Number Definitions */ typedef enum IRQn { /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ /* Device specific interrupts */ DMA0_DMA16_IRQn = 0, /**< DMA channel 0/16 transfer complete interrupt */ DMA1_DMA17_IRQn = 1, /**< DMA channel 1/17 transfer complete interrupt */ DMA2_DMA18_IRQn = 2, /**< DMA channel 2/18 transfer complete interrupt */ DMA3_DMA19_IRQn = 3, /**< DMA channel 3/19 transfer complete interrupt */ DMA4_DMA20_IRQn = 4, /**< DMA channel 4/20 transfer complete interrupt */ DMA5_DMA21_IRQn = 5, /**< DMA channel 5/21 transfer complete interrupt */ DMA6_DMA22_IRQn = 6, /**< DMA channel 6/22 transfer complete interrupt */ DMA7_DMA23_IRQn = 7, /**< DMA channel 7/23 transfer complete interrupt */ DMA8_DMA24_IRQn = 8, /**< DMA channel 8/24 transfer complete interrupt */ DMA9_DMA25_IRQn = 9, /**< DMA channel 9/25 transfer complete interrupt */ DMA10_DMA26_IRQn = 10, /**< DMA channel 10/26 transfer complete interrupt */ DMA11_DMA27_IRQn = 11, /**< DMA channel 11/27 transfer complete interrupt */ DMA12_DMA28_IRQn = 12, /**< DMA channel 12/28 transfer complete interrupt */ DMA13_DMA29_IRQn = 13, /**< DMA channel 13/29 transfer complete interrupt */ DMA14_DMA30_IRQn = 14, /**< DMA channel 14/30 transfer complete interrupt */ DMA15_DMA31_IRQn = 15, /**< DMA channel 15/31 transfer complete interrupt */ DMA_Error_IRQn = 16, /**< DMA error interrupt */ MCM_IRQn = 17, /**< Normal interrupt */ FTFE_IRQn = 18, /**< FTFE interrupt */ Read_Collision_IRQn = 19, /**< Read collision interrupt */ LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ LLW_IRQn = 21, /**< Low Leakage Wakeup */ Watchdog_IRQn = 22, /**< WDOG interrupt */ RNG_IRQn = 23, /**< RNGB interrupt */ I2C0_IRQn = 24, /**< I2C0 interrupt */ I2C1_IRQn = 25, /**< I2C1 interrupt */ SPI0_IRQn = 26, /**< SPI0 interrupt */ SPI1_IRQn = 27, /**< SPI1 interrupt */ SPI2_IRQn = 28, /**< SPI2 interrupt */ CAN0_ORed_Message_buffer_IRQn = 29, /**< CAN0 OR'd message buffers interrupt */ CAN0_Bus_Off_IRQn = 30, /**< CAN0 bus off interrupt */ CAN0_Error_IRQn = 31, /**< CAN0 error interrupt */ CAN0_Tx_Warning_IRQn = 32, /**< CAN0 Tx warning interrupt */ CAN0_Rx_Warning_IRQn = 33, /**< CAN0 Rx warning interrupt */ CAN0_Wake_Up_IRQn = 34, /**< CAN0 wake up interrupt */ I2S0_Tx_IRQn = 35, /**< I2S0 transmit interrupt */ I2S0_Rx_IRQn = 36, /**< I2S0 receive interrupt */ CAN1_ORed_Message_buffer_IRQn = 37, /**< CAN1 OR'd message buffers interrupt */ CAN1_Bus_Off_IRQn = 38, /**< CAN1 bus off interrupt */ CAN1_Error_IRQn = 39, /**< CAN1 error interrupt */ CAN1_Tx_Warning_IRQn = 40, /**< CAN1 Tx warning interrupt */ CAN1_Rx_Warning_IRQn = 41, /**< CAN1 Rx warning interrupt */ CAN1_Wake_Up_IRQn = 42, /**< CAN1 wake up interrupt */ Reserved59_IRQn = 43, /**< Reserved interrupt 59 */ UART0_LON_IRQn = 44, /**< UART0 LON interrupt */ UART0_RX_TX_IRQn = 45, /**< UART0 receive/transmit interrupt */ UART0_ERR_IRQn = 46, /**< UART0 error interrupt */ UART1_RX_TX_IRQn = 47, /**< UART1 receive/transmit interrupt */ UART1_ERR_IRQn = 48, /**< UART1 error interrupt */ UART2_RX_TX_IRQn = 49, /**< UART2 receive/transmit interrupt */ UART2_ERR_IRQn = 50, /**< UART2 error interrupt */ UART3_RX_TX_IRQn = 51, /**< UART3 receive/transmit interrupt */ UART3_ERR_IRQn = 52, /**< UART3 error interrupt */ UART4_RX_TX_IRQn = 53, /**< UART4 receive/transmit interrupt */ UART4_ERR_IRQn = 54, /**< UART4 error interrupt */ UART5_RX_TX_IRQn = 55, /**< UART5 receive/transmit interrupt */ UART5_ERR_IRQn = 56, /**< UART5 error interrupt */ ADC0_IRQn = 57, /**< ADC0 interrupt */ ADC1_IRQn = 58, /**< ADC1 interrupt */ CMP0_IRQn = 59, /**< CMP0 interrupt */ CMP1_IRQn = 60, /**< CMP1 interrupt */ CMP2_IRQn = 61, /**< CMP2 interrupt */ FTM0_IRQn = 62, /**< FTM0 fault, overflow and channels interrupt */ FTM1_IRQn = 63, /**< FTM1 fault, overflow and channels interrupt */ FTM2_IRQn = 64, /**< FTM2 fault, overflow and channels interrupt */ CMT_IRQn = 65, /**< CMT interrupt */ RTC_IRQn = 66, /**< RTC interrupt */ RTC_Seconds_IRQn = 67, /**< RTC seconds interrupt */ PIT0_IRQn = 68, /**< PIT timer channel 0 interrupt */ PIT1_IRQn = 69, /**< PIT timer channel 1 interrupt */ PIT2_IRQn = 70, /**< PIT timer channel 2 interrupt */ PIT3_IRQn = 71, /**< PIT timer channel 3 interrupt */ PDB0_IRQn = 72, /**< PDB0 interrupt */ USB0_IRQn = 73, /**< USB0 interrupt */ USBDCD_IRQn = 74, /**< USBDCD interrupt */ ENET_1588_Timer_IRQn = 75, /**< Ethernet MAC IEEE 1588 timer interrupt */ ENET_Transmit_IRQn = 76, /**< Ethernet MAC transmit interrupt */ ENET_Receive_IRQn = 77, /**< Ethernet MAC receive interrupt */ ENET_Error_IRQn = 78, /**< Ethernet MAC error and miscelaneous interrupt */ Reserved95_IRQn = 79, /**< Reserved interrupt 95 */ SDHC_IRQn = 80, /**< SDHC interrupt */ DAC0_IRQn = 81, /**< DAC0 interrupt */ DAC1_IRQn = 82, /**< DAC1 interrupt */ TSI0_IRQn = 83, /**< TSI0 interrupt */ MCG_IRQn = 84, /**< MCG interrupt */ LPTimer_IRQn = 85, /**< LPTimer interrupt */ Reserved102_IRQn = 86, /**< Reserved interrupt 102 */ PORTA_IRQn = 87, /**< Port A interrupt */ PORTB_IRQn = 88, /**< Port B interrupt */ PORTC_IRQn = 89, /**< Port C interrupt */ PORTD_IRQn = 90, /**< Port D interrupt */ PORTE_IRQn = 91, /**< Port E interrupt */ PORTF_IRQn = 92, /**< Port F interrupt */ Reserved109_IRQn = 93, /**< Reserved interrupt 109 */ SWI_IRQn = 94, /**< Software interrupt */ NFC_IRQn = 95, /**< NAND flash controller interrupt */ USBHS_IRQn = 96, /**< USB high speed OTG interrupt */ Reserved113_IRQn = 97, /**< Reserved interrupt 113 */ CMP3_IRQn = 98, /**< CMP3 interrupt */ Reserved115_IRQn = 99, /**< Reserved interrupt 115 */ Reserved116_IRQn = 100, /**< Reserved interrupt 116 */ FTM3_IRQn = 101, /**< FTM3 fault, overflow and channels interrupt */ ADC2_IRQn = 102, /**< ADC2 interrupt */ ADC3_IRQn = 103, /**< ADC3 interrupt */ I2S1_Tx_IRQn = 104, /**< I2S1 transmit interrupt */ I2S1_Rx_IRQn = 105 /**< I2S1 receive interrupt */ } IRQn_Type; /** * @} */ /* end of group Interrupt_vector_numbers */ /* ---------------------------------------------------------------------------- -- Configuration of the Cortex-M4 Processor and Core Peripherals ---------------------------------------------------------------------------- */ /** * @addtogroup Cortex_Core_Configuration Configuration of the Cortex-M4 Processor and Core Peripherals * @{ */ #define __CM4_REV 0x0001 /**< Core revision r0p1 */ #define __MPU_PRESENT 0 /**< MPU present or not */ #define __NVIC_PRIO_BITS 4 /**< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1 /**< FPU present or not */ #include "core_cm4.h" /* Core Peripheral Access Layer */ #include "system_MK60F15.h" /* Device specific configuration file */ /** * @} */ /* end of group Cortex_Core_Configuration */ /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ /** * @addtogroup Peripheral_access_layer Device Peripheral Access Layer * @{ */ /* ** Start of section using anonymous unions */ #if defined(__ARMCC_VERSION) #pragma push #pragma anon_unions #elif defined(__CWCC__) #pragma push #pragma cpp_extensions on #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=extended #else #error Not supported compiler type #endif /* ---------------------------------------------------------------------------- -- ADC Peripheral Access Layer ---------------------------------------------------------------------------- */ /** * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer * @{ */ /** ADC - Register Layout Typedef */ typedef struct { __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */ __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */ __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */ __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */ __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */ __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */ __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */ __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */ __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */ __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */ __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */ __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */ __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */ __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */ __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */ __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */ __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */ __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */ __IO uint32_t PGA; /**< ADC PGA register, offset: 0x50 */ __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */ __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */ __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */ __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */ __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */ __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */ __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */ } ADC_Type; /* ---------------------------------------------------------------------------- -- ADC Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup ADC_Register_Masks ADC Register Masks * @{ */ /* SC1 Bit Fields */ #define ADC_SC1_ADCH_MASK 0x1Fu #define ADC_SC1_ADCH_SHIFT 0 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))< MAX_FL bytes, good CRC (RMON_T_OVERSIZE), offset: 0x218 */ __IO uint32_t RMON_T_FRAG; /**< RMON Tx Packets < 64 bytes, bad CRC (RMON_T_FRAG), offset: 0x21C */ __IO uint32_t RMON_T_JAB; /**< RMON Tx Packets > MAX_FL bytes, bad CRC (RMON_T_JAB), offset: 0x220 */ __IO uint32_t RMON_T_COL; /**< RMON Tx collision count (RMON_T_COL), offset: 0x224 */ __IO uint32_t RMON_T_P64; /**< RMON Tx 64 byte packets (RMON_T_P64), offset: 0x228 */ __IO uint32_t RMON_T_P65TO127; /**< RMON Tx 65 to 127 byte packets (RMON_T_P65TO127), offset: 0x22C */ __IO uint32_t RMON_T_P128TO255; /**< RMON Tx 128 to 255 byte packets (RMON_T_P128TO255), offset: 0x230 */ __IO uint32_t RMON_T_P256TO511; /**< RMON Tx 256 to 511 byte packets (RMON_T_P256TO511), offset: 0x234 */ __IO uint32_t RMON_T_P512TO1023; /**< RMON Tx 512 to 1023 byte packets (RMON_T_P512TO1023), offset: 0x238 */ __IO uint32_t RMON_T_P1024TO2047; /**< RMON Tx 1024 to 2047 byte packets (RMON_T_P1024TO2047), offset: 0x23C */ __IO uint32_t RMON_T_P_GTE2048; /**< RMON Tx packets w > 2048 bytes (RMON_T_P_GTE2048), offset: 0x240 */ __IO uint32_t RMON_T_OCTETS; /**< RMON Tx Octets (RMON_T_OCTETS), offset: 0x244 */ __IO uint32_t IEEE_T_DROP; /**< Count of frames not counted correctly (IEEE_T_DROP). NOTE: Counter not implemented (read 0 always) as not applicable., offset: 0x248 */ __IO uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK (IEEE_T_FRAME_OK), offset: 0x24C */ __IO uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision (IEEE_T_1COL), offset: 0x250 */ __IO uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions (IEEE_T_MCOL), offset: 0x254 */ __IO uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay (IEEE_T_DEF), offset: 0x258 */ __IO uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision (IEEE_T_LCOL), offset: 0x25C */ __IO uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions (IEEE_T_EXCOL), offset: 0x260 */ __IO uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun (IEEE_T_MACERR), offset: 0x264 */ __IO uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error (IEEE_T_CSERR), offset: 0x268 */ __IO uint32_t IEEE_T_SQE; /**< Frames Transmitted with SQE Error (IEEE_T_SQE). NOTE: Counter not implemented (read 0 always) as no SQE information is available., offset: 0x26C */ __IO uint32_t IEEE_T_FDXFC; /**< Flow Control Pause frames transmitted (IEEE_T_FDXFC), offset: 0x270 */ __IO uint32_t IEEE_T_OCTETS_OK; /**< Octet count for Frames Transmitted w/o Error (IEEE_T_OCTETS_OK). NOTE: Counts total octets (includes header and FCS fields)., offset: 0x274 */ uint8_t RESERVED_14[12]; __IO uint32_t RMON_R_PACKETS; /**< RMON Rx packet count (RMON_R_PACKETS), offset: 0x284 */ __IO uint32_t RMON_R_BC_PKT; /**< RMON Rx Broadcast Packets (RMON_R_BC_PKT), offset: 0x288 */ __IO uint32_t RMON_R_MC_PKT; /**< RMON Rx Multicast Packets (RMON_R_MC_PKT), offset: 0x28C */ __IO uint32_t RMON_R_CRC_ALIGN; /**< RMON Rx Packets w CRC/Align error (RMON_R_CRC_ALIGN), offset: 0x290 */ __IO uint32_t RMON_R_UNDERSIZE; /**< RMON Rx Packets < 64 bytes, good CRC (RMON_R_UNDERSIZE), offset: 0x294 */ __IO uint32_t RMON_R_OVERSIZE; /**< RMON Rx Packets > MAX_FL bytes, good CRC (RMON_R_OVERSIZE), offset: 0x298 */ __IO uint32_t RMON_R_FRAG; /**< RMON Rx Packets < 64 bytes, bad CRC (RMON_R_FRAG), offset: 0x29C */ __IO uint32_t RMON_R_JAB; /**< RMON Rx Packets > MAX_FL bytes, bad CRC (RMON_R_JAB), offset: 0x2A0 */ __IO uint32_t RMON_R_RESVD_0; /**< Reserved (RMON_R_RESVD_0), offset: 0x2A4 */ __IO uint32_t RMON_R_P64; /**< RMON Rx 64 byte packets (RMON_R_P64), offset: 0x2A8 */ __IO uint32_t RMON_R_P65TO127; /**< RMON Rx 65 to 127 byte packets (RMON_R_P65TO127), offset: 0x2AC */ __IO uint32_t RMON_R_P128TO255; /**< RMON Rx 128 to 255 byte packets (RMON_R_P128TO255), offset: 0x2B0 */ __IO uint32_t RMON_R_P256TO511; /**< RMON Rx 256 to 511 byte packets (RMON_R_P256TO511), offset: 0x2B4 */ __IO uint32_t RMON_R_P512TO1023; /**< RMON Rx 512 to 1023 byte packets (RMON_R_P512TO1023), offset: 0x2B8 */ __IO uint32_t RMON_R_P1024TO2047; /**< RMON Rx 1024 to 2047 byte packets (RMON_R_P1024TO2047), offset: 0x2BC */ __IO uint32_t RMON_R_P_GTE2048; /**< RMON Rx packets w > 2048 bytes (RMON_R_P_GTE2048), offset: 0x2C0 */ __IO uint32_t RMON_R_OCTETS; /**< RMON Rx Octets (RMON_R_OCTETS), offset: 0x2C4 */ __IO uint32_t RMON_R_DROP; /**< Count of frames not counted correctly (IEEE_R_DROP). NOTE: Counter increments if a frame with valid/missing SFD character is detected and has been dropped. None of the other counters increments if this counter increments., offset: 0x2C8 */ __IO uint32_t RMON_R_FRAME_OK; /**< Frames Received OK (IEEE_R_FRAME_OK), offset: 0x2CC */ __IO uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error (IEEE_R_CRC), offset: 0x2D0 */ __IO uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error (IEEE_R_ALIGN), offset: 0x2D4 */ __IO uint32_t IEEE_R_MACERR; /**< Receive Fifo Overflow count (IEEE_R_MACERR), offset: 0x2D8 */ __IO uint32_t IEEE_R_FDXFC; /**< Flow Control Pause frames received (IEEE_R_FDXFC), offset: 0x2DC */ __IO uint32_t IEEE_R_OCTETS_OK; /**< Octet count for Frames Rcvd w/o Error (IEEE_R_OCTETS_OK). Counts total octets (includes header and FCS fields)., offset: 0x2E0 */ uint8_t RESERVED_15[284]; __IO uint32_t ATCR; /**< Timer Control Register, offset: 0x400 */ __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ __IO uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ uint8_t RESERVED_16[488]; __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ struct { /* offset: 0x608, array step: 0x8 */ __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ } CHANNEL[4]; } ENET_Type; /* ---------------------------------------------------------------------------- -- ENET Register Masks ---------------------------------------------------------------------------- */ /** * @addtogroup ENET_Register_Masks ENET Register Masks * @{ */ /* EIR Bit Fields */ #define ENET_EIR_TS_TIMER_MASK 0x8000u #define ENET_EIR_TS_TIMER_SHIFT 15 #define ENET_EIR_TS_AVAIL_MASK 0x10000u #define ENET_EIR_TS_AVAIL_SHIFT 16 #define ENET_EIR_WAKEUP_MASK 0x20000u #define ENET_EIR_WAKEUP_SHIFT 17 #define ENET_EIR_PLR_MASK 0x40000u #define ENET_EIR_PLR_SHIFT 18 #define ENET_EIR_UN_MASK 0x80000u #define ENET_EIR_UN_SHIFT 19 #define ENET_EIR_RL_MASK 0x100000u #define ENET_EIR_RL_SHIFT 20 #define ENET_EIR_LC_MASK 0x200000u #define ENET_EIR_LC_SHIFT 21 #define ENET_EIR_EBERR_MASK 0x400000u #define ENET_EIR_EBERR_SHIFT 22 #define ENET_EIR_MII_MASK 0x800000u #define ENET_EIR_MII_SHIFT 23 #define ENET_EIR_RXB_MASK 0x1000000u #define ENET_EIR_RXB_SHIFT 24 #define ENET_EIR_RXF_MASK 0x2000000u #define ENET_EIR_RXF_SHIFT 25 #define ENET_EIR_TXB_MASK 0x4000000u #define ENET_EIR_TXB_SHIFT 26 #define ENET_EIR_TXF_MASK 0x8000000u #define ENET_EIR_TXF_SHIFT 27 #define ENET_EIR_GRA_MASK 0x10000000u #define ENET_EIR_GRA_SHIFT 28 #define ENET_EIR_BABT_MASK 0x20000000u #define ENET_EIR_BABT_SHIFT 29 #define ENET_EIR_BABR_MASK 0x40000000u #define ENET_EIR_BABR_SHIFT 30 /* EIMR Bit Fields */ #define ENET_EIMR_TS_TIMER_MASK 0x8000u #define ENET_EIMR_TS_TIMER_SHIFT 15 #define ENET_EIMR_TS_AVAIL_MASK 0x10000u #define ENET_EIMR_TS_AVAIL_SHIFT 16 #define ENET_EIMR_WAKEUP_MASK 0x20000u #define ENET_EIMR_WAKEUP_SHIFT 17 #define ENET_EIMR_PLR_MASK 0x40000u #define ENET_EIMR_PLR_SHIFT 18 #define ENET_EIMR_UN_MASK 0x80000u #define ENET_EIMR_UN_SHIFT 19 #define ENET_EIMR_RL_MASK 0x100000u #define ENET_EIMR_RL_SHIFT 20 #define ENET_EIMR_LC_MASK 0x200000u #define ENET_EIMR_LC_SHIFT 21 #define ENET_EIMR_EBERR_MASK 0x400000u #define ENET_EIMR_EBERR_SHIFT 22 #define ENET_EIMR_MII_MASK 0x800000u #define ENET_EIMR_MII_SHIFT 23 #define ENET_EIMR_RXB_MASK 0x1000000u #define ENET_EIMR_RXB_SHIFT 24 #define ENET_EIMR_RXF_MASK 0x2000000u #define ENET_EIMR_RXF_SHIFT 25 #define ENET_EIMR_TXB_MASK 0x4000000u #define ENET_EIMR_TXB_SHIFT 26 #define ENET_EIMR_TXF_MASK 0x8000000u #define ENET_EIMR_TXF_SHIFT 27 #define ENET_EIMR_GRA_MASK 0x10000000u #define ENET_EIMR_GRA_SHIFT 28 #define ENET_EIMR_BABT_MASK 0x20000000u #define ENET_EIMR_BABT_SHIFT 29 #define ENET_EIMR_BABR_MASK 0x40000000u #define ENET_EIMR_BABR_SHIFT 30 /* RDAR Bit Fields */ #define ENET_RDAR_RDAR_MASK 0x1000000u #define ENET_RDAR_RDAR_SHIFT 24 /* TDAR Bit Fields */ #define ENET_TDAR_TDAR_MASK 0x1000000u #define ENET_TDAR_TDAR_SHIFT 24 /* ECR Bit Fields */ #define ENET_ECR_RESET_MASK 0x1u #define ENET_ECR_RESET_SHIFT 0 #define ENET_ECR_ETHEREN_MASK 0x2u #define ENET_ECR_ETHEREN_SHIFT 1 #define ENET_ECR_MAGICEN_MASK 0x4u #define ENET_ECR_MAGICEN_SHIFT 2 #define ENET_ECR_SLEEP_MASK 0x8u #define ENET_ECR_SLEEP_SHIFT 3 #define ENET_ECR_EN1588_MASK 0x10u #define ENET_ECR_EN1588_SHIFT 4 #define ENET_ECR_DBGEN_MASK 0x40u #define ENET_ECR_DBGEN_SHIFT 6 #define ENET_ECR_STOPEN_MASK 0x80u #define ENET_ECR_STOPEN_SHIFT 7 #define ENET_ECR_DBSWP_MASK 0x100u #define ENET_ECR_DBSWP_SHIFT 8 /* MMFR Bit Fields */ #define ENET_MMFR_DATA_MASK 0xFFFFu #define ENET_MMFR_DATA_SHIFT 0 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<