// ---------------------------------------------------------------------------- // ATMEL Microcontroller Software Support - ROUSSET - // ---------------------------------------------------------------------------- // Copyright (c) 2006, Atmel Corporation // // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // // - Redistributions of source code must retain the above copyright notice, // this list of conditions and the disclaimer below. // // - Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the disclaimer below in the documentation and/or // other materials provided with the distribution. // // Atmel's name may not be used to endorse or promote products derived from // this software without specific prior written permission. // // DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR // IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE // DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, // OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, // EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // ---------------------------------------------------------------------------- // File Name : AT91SAM9263.h // Object : AT91SAM9263 definitions // Generated : AT91 SW Application Group 12/07/2006 (13:32:18) // // CVS Reference : /AT91SAM9263.pl/1.2/Fri Nov 10 12:56:00 2006// // CVS Reference : /SYS_SAM9262.pl/1.4/Tue Jan 18 17:06:33 2005// // CVS Reference : /HMATRIX1_SAM9262.pl/1.10/Thu Oct 13 12:44:26 2005// // CVS Reference : /CCR_SAM9262.pl/1.7/Fri Nov 10 13:23:00 2006// // CVS Reference : /PMC_SAM9262.pl/1.4/Mon Mar 7 18:03:13 2005// // CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 9 10:52:25 2004// // CVS Reference : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004// // CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// // CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// // CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// // CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// // CVS Reference : /RSTC_6098A.pl/1.3/Thu Nov 4 13:57:00 2004// // CVS Reference : /SHDWC_6122A.pl/1.3/Wed Oct 6 14:16:58 2004// // CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// // CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// // CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// // CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// // CVS Reference : /MCI_6101E.pl/1.1/Fri Jun 3 13:20:23 2005// // CVS Reference : /TWI_6061A.pl/1.2/Wed Oct 25 15:03:34 2006// // CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// // CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:25:46 2005// // CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// // CVS Reference : /AC97C_XXXX.pl/1.3/Tue Feb 22 17:08:27 2005// // CVS Reference : /CAN_6019B.pl/1.1/Mon Jan 31 13:54:30 2005// // CVS Reference : /PWM_6044D.pl/1.2/Tue May 10 12:39:09 2005// // CVS Reference : /LCDC_6063A.pl/1.3/Fri Dec 9 10:59:26 2005// // CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005// // CVS Reference : /DMA_XXXX.pl/1.6/Tue Jan 11 09:40:44 2005// // CVS Reference : /UDP_6ept_puon.pl/1.1/Wed Aug 30 14:20:53 2006// // CVS Reference : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005// // CVS Reference : /TBOX_XXXX.pl/1.15/Thu Jun 9 07:05:57 2005// // CVS Reference : /EBI_nadia2.pl/1.1/Wed Dec 29 11:28:03 2004// // CVS Reference : /HECC_6143A.pl/1.1/Wed Feb 9 17:16:57 2005// // CVS Reference : /ISI_xxxxx.pl/1.3/Thu Mar 3 11:11:48 2005// // ---------------------------------------------------------------------------- #ifndef AT91SAM9263_H #define AT91SAM9263_H #ifndef __ASSEMBLY__ typedef volatile unsigned int AT91_REG;// Hardware register definition #define AT91_CAST(a) (a) #else #define AT91_CAST(a) #endif // ***************************************************************************** // SOFTWARE API DEFINITION FOR System Peripherals // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_SYS { AT91_REG SYS_ECC0; // ECC 0 AT91_REG Reserved0[127]; // AT91_REG SYS_SDRAMC0_MR; // SDRAM Controller Mode Register AT91_REG SYS_SDRAMC0_TR; // SDRAM Controller Refresh Timer Register AT91_REG SYS_SDRAMC0_CR; // SDRAM Controller Configuration Register AT91_REG SYS_SDRAMC0_HSR; // SDRAM Controller High Speed Register AT91_REG SYS_SDRAMC0_LPR; // SDRAM Controller Low Power Register AT91_REG SYS_SDRAMC0_IER; // SDRAM Controller Interrupt Enable Register AT91_REG SYS_SDRAMC0_IDR; // SDRAM Controller Interrupt Disable Register AT91_REG SYS_SDRAMC0_IMR; // SDRAM Controller Interrupt Mask Register AT91_REG SYS_SDRAMC0_ISR; // SDRAM Controller Interrupt Mask Register AT91_REG SYS_SDRAMC0_MDR; // SDRAM Memory Device Register AT91_REG Reserved1[118]; // AT91_REG SYS_SMC0_SETUP0; // Setup Register for CS 0 AT91_REG SYS_SMC0_PULSE0; // Pulse Register for CS 0 AT91_REG SYS_SMC0_CYCLE0; // Cycle Register for CS 0 AT91_REG SYS_SMC0_CTRL0; // Control Register for CS 0 AT91_REG SYS_SMC0_SETUP1; // Setup Register for CS 1 AT91_REG SYS_SMC0_PULSE1; // Pulse Register for CS 1 AT91_REG SYS_SMC0_CYCLE1; // Cycle Register for CS 1 AT91_REG SYS_SMC0_CTRL1; // Control Register for CS 1 AT91_REG SYS_SMC0_SETUP2; // Setup Register for CS 2 AT91_REG SYS_SMC0_PULSE2; // Pulse Register for CS 2 AT91_REG SYS_SMC0_CYCLE2; // Cycle Register for CS 2 AT91_REG SYS_SMC0_CTRL2; // Control Register for CS 2 AT91_REG SYS_SMC0_SETUP3; // Setup Register for CS 3 AT91_REG SYS_SMC0_PULSE3; // Pulse Register for CS 3 AT91_REG SYS_SMC0_CYCLE3; // Cycle Register for CS 3 AT91_REG SYS_SMC0_CTRL3; // Control Register for CS 3 AT91_REG SYS_SMC0_SETUP4; // Setup Register for CS 4 AT91_REG SYS_SMC0_PULSE4; // Pulse Register for CS 4 AT91_REG SYS_SMC0_CYCLE4; // Cycle Register for CS 4 AT91_REG SYS_SMC0_CTRL4; // Control Register for CS 4 AT91_REG SYS_SMC0_SETUP5; // Setup Register for CS 5 AT91_REG SYS_SMC0_PULSE5; // Pulse Register for CS 5 AT91_REG SYS_SMC0_CYCLE5; // Cycle Register for CS 5 AT91_REG SYS_SMC0_CTRL5; // Control Register for CS 5 AT91_REG SYS_SMC0_SETUP6; // Setup Register for CS 6 AT91_REG SYS_SMC0_PULSE6; // Pulse Register for CS 6 AT91_REG SYS_SMC0_CYCLE6; // Cycle Register for CS 6 AT91_REG SYS_SMC0_CTRL6; // Control Register for CS 6 AT91_REG SYS_SMC0_SETUP7; // Setup Register for CS 7 AT91_REG SYS_SMC0_PULSE7; // Pulse Register for CS 7 AT91_REG SYS_SMC0_CYCLE7; // Cycle Register for CS 7 AT91_REG SYS_SMC0_CTRL7; // Control Register for CS 7 AT91_REG Reserved2[96]; // AT91_REG SYS_ECC1; // ECC 0 AT91_REG Reserved3[127]; // AT91_REG SYS_SDRAMC1_MR; // SDRAM Controller Mode Register AT91_REG SYS_SDRAMC1_TR; // SDRAM Controller Refresh Timer Register AT91_REG SYS_SDRAMC1_CR; // SDRAM Controller Configuration Register AT91_REG SYS_SDRAMC1_HSR; // SDRAM Controller High Speed Register AT91_REG SYS_SDRAMC1_LPR; // SDRAM Controller Low Power Register AT91_REG SYS_SDRAMC1_IER; // SDRAM Controller Interrupt Enable Register AT91_REG SYS_SDRAMC1_IDR; // SDRAM Controller Interrupt Disable Register AT91_REG SYS_SDRAMC1_IMR; // SDRAM Controller Interrupt Mask Register AT91_REG SYS_SDRAMC1_ISR; // SDRAM Controller Interrupt Mask Register AT91_REG SYS_SDRAMC1_MDR; // SDRAM Memory Device Register AT91_REG Reserved4[118]; // AT91_REG SYS_SMC1_SETUP0; // Setup Register for CS 0 AT91_REG SYS_SMC1_PULSE0; // Pulse Register for CS 0 AT91_REG SYS_SMC1_CYCLE0; // Cycle Register for CS 0 AT91_REG SYS_SMC1_CTRL0; // Control Register for CS 0 AT91_REG SYS_SMC1_SETUP1; // Setup Register for CS 1 AT91_REG SYS_SMC1_PULSE1; // Pulse Register for CS 1 AT91_REG SYS_SMC1_CYCLE1; // Cycle Register for CS 1 AT91_REG SYS_SMC1_CTRL1; // Control Register for CS 1 AT91_REG SYS_SMC1_SETUP2; // Setup Register for CS 2 AT91_REG SYS_SMC1_PULSE2; // Pulse Register for CS 2 AT91_REG SYS_SMC1_CYCLE2; // Cycle Register for CS 2 AT91_REG SYS_SMC1_CTRL2; // Control Register for CS 2 AT91_REG SYS_SMC1_SETUP3; // Setup Register for CS 3 AT91_REG SYS_SMC1_PULSE3; // Pulse Register for CS 3 AT91_REG SYS_SMC1_CYCLE3; // Cycle Register for CS 3 AT91_REG SYS_SMC1_CTRL3; // Control Register for CS 3 AT91_REG SYS_SMC1_SETUP4; // Setup Register for CS 4 AT91_REG SYS_SMC1_PULSE4; // Pulse Register for CS 4 AT91_REG SYS_SMC1_CYCLE4; // Cycle Register for CS 4 AT91_REG SYS_SMC1_CTRL4; // Control Register for CS 4 AT91_REG SYS_SMC1_SETUP5; // Setup Register for CS 5 AT91_REG SYS_SMC1_PULSE5; // Pulse Register for CS 5 AT91_REG SYS_SMC1_CYCLE5; // Cycle Register for CS 5 AT91_REG SYS_SMC1_CTRL5; // Control Register for CS 5 AT91_REG SYS_SMC1_SETUP6; // Setup Register for CS 6 AT91_REG SYS_SMC1_PULSE6; // Pulse Register for CS 6 AT91_REG SYS_SMC1_CYCLE6; // Cycle Register for CS 6 AT91_REG SYS_SMC1_CTRL6; // Control Register for CS 6 AT91_REG SYS_SMC1_SETUP7; // Setup Register for CS 7 AT91_REG SYS_SMC1_PULSE7; // Pulse Register for CS 7 AT91_REG SYS_SMC1_CYCLE7; // Cycle Register for CS 7 AT91_REG SYS_SMC1_CTRL7; // Control Register for CS 7 AT91_REG Reserved5[96]; // AT91_REG SYS_MATRIX_MCFG0; // Master Configuration Register 0 AT91_REG SYS_MATRIX_MCFG1; // Master Configuration Register 1 AT91_REG SYS_MATRIX_MCFG2; // Master Configuration Register 2 AT91_REG SYS_MATRIX_MCFG3; // Master Configuration Register 3 AT91_REG SYS_MATRIX_MCFG4; // Master Configuration Register 4 AT91_REG SYS_MATRIX_MCFG5; // Master Configuration Register 5 AT91_REG SYS_MATRIX_MCFG6; // Master Configuration Register 6 AT91_REG SYS_MATRIX_MCFG7; // Master Configuration Register 7 AT91_REG SYS_MATRIX_MCFG8; // Master Configuration Register 8 AT91_REG Reserved6[7]; // AT91_REG SYS_MATRIX_SCFG0; // Slave Configuration Register 0 AT91_REG SYS_MATRIX_SCFG1; // Slave Configuration Register 1 AT91_REG SYS_MATRIX_SCFG2; // Slave Configuration Register 2 AT91_REG SYS_MATRIX_SCFG3; // Slave Configuration Register 3 AT91_REG SYS_MATRIX_SCFG4; // Slave Configuration Register 4 AT91_REG SYS_MATRIX_SCFG5; // Slave Configuration Register 5 AT91_REG SYS_MATRIX_SCFG6; // Slave Configuration Register 6 AT91_REG SYS_MATRIX_SCFG7; // Slave Configuration Register 7 AT91_REG Reserved7[8]; // AT91_REG SYS_MATRIX_PRAS0; // PRAS0 AT91_REG SYS_MATRIX_PRBS0; // PRBS0 AT91_REG SYS_MATRIX_PRAS1; // PRAS1 AT91_REG SYS_MATRIX_PRBS1; // PRBS1 AT91_REG SYS_MATRIX_PRAS2; // PRAS2 AT91_REG SYS_MATRIX_PRBS2; // PRBS2 AT91_REG SYS_MATRIX_PRAS3; // PRAS3 AT91_REG SYS_MATRIX_PRBS3; // PRBS3 AT91_REG SYS_MATRIX_PRAS4; // PRAS4 AT91_REG SYS_MATRIX_PRBS4; // PRBS4 AT91_REG SYS_MATRIX_PRAS5; // PRAS5 AT91_REG SYS_MATRIX_PRBS5; // PRBS5 AT91_REG SYS_MATRIX_PRAS6; // PRAS6 AT91_REG SYS_MATRIX_PRBS6; // PRBS6 AT91_REG SYS_MATRIX_PRAS7; // PRAS7 AT91_REG SYS_MATRIX_PRBS7; // PRBS7 AT91_REG Reserved8[16]; // AT91_REG SYS_MATRIX_MRCR; // Master Remp Control Register AT91_REG Reserved9[63]; // AT91_REG SYS_DBGU_CR; // Control Register AT91_REG SYS_DBGU_MR; // Mode Register AT91_REG SYS_DBGU_IER; // Interrupt Enable Register AT91_REG SYS_DBGU_IDR; // Interrupt Disable Register AT91_REG SYS_DBGU_IMR; // Interrupt Mask Register AT91_REG SYS_DBGU_CSR; // Channel Status Register AT91_REG SYS_DBGU_RHR; // Receiver Holding Register AT91_REG SYS_DBGU_THR; // Transmitter Holding Register AT91_REG SYS_DBGU_BRGR; // Baud Rate Generator Register AT91_REG Reserved10[7]; // AT91_REG SYS_DBGU_CIDR; // Chip ID Register AT91_REG SYS_DBGU_EXID; // Chip ID Extension Register AT91_REG SYS_DBGU_FNTR; // Force NTRST Register AT91_REG Reserved11[45]; // AT91_REG SYS_DBGU_RPR; // Receive Pointer Register AT91_REG SYS_DBGU_RCR; // Receive Counter Register AT91_REG SYS_DBGU_TPR; // Transmit Pointer Register AT91_REG SYS_DBGU_TCR; // Transmit Counter Register AT91_REG SYS_DBGU_RNPR; // Receive Next Pointer Register AT91_REG SYS_DBGU_RNCR; // Receive Next Counter Register AT91_REG SYS_DBGU_TNPR; // Transmit Next Pointer Register AT91_REG SYS_DBGU_TNCR; // Transmit Next Counter Register AT91_REG SYS_DBGU_PTCR; // PDC Transfer Control Register AT91_REG SYS_DBGU_PTSR; // PDC Transfer Status Register AT91_REG Reserved12[54]; // AT91_REG SYS_AIC_SMR[32]; // Source Mode Register AT91_REG SYS_AIC_SVR[32]; // Source Vector Register AT91_REG SYS_AIC_IVR; // IRQ Vector Register AT91_REG SYS_AIC_FVR; // FIQ Vector Register AT91_REG SYS_AIC_ISR; // Interrupt Status Register AT91_REG SYS_AIC_IPR; // Interrupt Pending Register AT91_REG SYS_AIC_IMR; // Interrupt Mask Register AT91_REG SYS_AIC_CISR; // Core Interrupt Status Register AT91_REG Reserved13[2]; // AT91_REG SYS_AIC_IECR; // Interrupt Enable Command Register AT91_REG SYS_AIC_IDCR; // Interrupt Disable Command Register AT91_REG SYS_AIC_ICCR; // Interrupt Clear Command Register AT91_REG SYS_AIC_ISCR; // Interrupt Set Command Register AT91_REG SYS_AIC_EOICR; // End of Interrupt Command Register AT91_REG SYS_AIC_SPU; // Spurious Vector Register AT91_REG SYS_AIC_DCR; // Debug Control Register (Protect) AT91_REG Reserved14[1]; // AT91_REG SYS_AIC_FFER; // Fast Forcing Enable Register AT91_REG SYS_AIC_FFDR; // Fast Forcing Disable Register AT91_REG SYS_AIC_FFSR; // Fast Forcing Status Register AT91_REG Reserved15[45]; // AT91_REG SYS_PIOA_PER; // PIO Enable Register AT91_REG SYS_PIOA_PDR; // PIO Disable Register AT91_REG SYS_PIOA_PSR; // PIO Status Register AT91_REG Reserved16[1]; // AT91_REG SYS_PIOA_OER; // Output Enable Register AT91_REG SYS_PIOA_ODR; // Output Disable Registerr AT91_REG SYS_PIOA_OSR; // Output Status Register AT91_REG Reserved17[1]; // AT91_REG SYS_PIOA_IFER; // Input Filter Enable Register AT91_REG SYS_PIOA_IFDR; // Input Filter Disable Register AT91_REG SYS_PIOA_IFSR; // Input Filter Status Register AT91_REG Reserved18[1]; // AT91_REG SYS_PIOA_SODR; // Set Output Data Register AT91_REG SYS_PIOA_CODR; // Clear Output Data Register AT91_REG SYS_PIOA_ODSR; // Output Data Status Register AT91_REG SYS_PIOA_PDSR; // Pin Data Status Register AT91_REG SYS_PIOA_IER; // Interrupt Enable Register AT91_REG SYS_PIOA_IDR; // Interrupt Disable Register AT91_REG SYS_PIOA_IMR; // Interrupt Mask Register AT91_REG SYS_PIOA_ISR; // Interrupt Status Register AT91_REG SYS_PIOA_MDER; // Multi-driver Enable Register AT91_REG SYS_PIOA_MDDR; // Multi-driver Disable Register AT91_REG SYS_PIOA_MDSR; // Multi-driver Status Register AT91_REG Reserved19[1]; // AT91_REG SYS_PIOA_PPUDR; // Pull-up Disable Register AT91_REG SYS_PIOA_PPUER; // Pull-up Enable Register AT91_REG SYS_PIOA_PPUSR; // Pull-up Status Register AT91_REG Reserved20[1]; // AT91_REG SYS_PIOA_ASR; // Select A Register AT91_REG SYS_PIOA_BSR; // Select B Register AT91_REG SYS_PIOA_ABSR; // AB Select Status Register AT91_REG Reserved21[9]; // AT91_REG SYS_PIOA_OWER; // Output Write Enable Register AT91_REG SYS_PIOA_OWDR; // Output Write Disable Register AT91_REG SYS_PIOA_OWSR; // Output Write Status Register AT91_REG Reserved22[85]; // AT91_REG SYS_PIOB_PER; // PIO Enable Register AT91_REG SYS_PIOB_PDR; // PIO Disable Register AT91_REG SYS_PIOB_PSR; // PIO Status Register AT91_REG Reserved23[1]; // AT91_REG SYS_PIOB_OER; // Output Enable Register AT91_REG SYS_PIOB_ODR; // Output Disable Registerr AT91_REG SYS_PIOB_OSR; // Output Status Register AT91_REG Reserved24[1]; // AT91_REG SYS_PIOB_IFER; // Input Filter Enable Register AT91_REG SYS_PIOB_IFDR; // Input Filter Disable Register AT91_REG SYS_PIOB_IFSR; // Input Filter Status Register AT91_REG Reserved25[1]; // AT91_REG SYS_PIOB_SODR; // Set Output Data Register AT91_REG SYS_PIOB_CODR; // Clear Output Data Register AT91_REG SYS_PIOB_ODSR; // Output Data Status Register AT91_REG SYS_PIOB_PDSR; // Pin Data Status Register AT91_REG SYS_PIOB_IER; // Interrupt Enable Register AT91_REG SYS_PIOB_IDR; // Interrupt Disable Register AT91_REG SYS_PIOB_IMR; // Interrupt Mask Register AT91_REG SYS_PIOB_ISR; // Interrupt Status Register AT91_REG SYS_PIOB_MDER; // Multi-driver Enable Register AT91_REG SYS_PIOB_MDDR; // Multi-driver Disable Register AT91_REG SYS_PIOB_MDSR; // Multi-driver Status Register AT91_REG Reserved26[1]; // AT91_REG SYS_PIOB_PPUDR; // Pull-up Disable Register AT91_REG SYS_PIOB_PPUER; // Pull-up Enable Register AT91_REG SYS_PIOB_PPUSR; // Pull-up Status Register AT91_REG Reserved27[1]; // AT91_REG SYS_PIOB_ASR; // Select A Register AT91_REG SYS_PIOB_BSR; // Select B Register AT91_REG SYS_PIOB_ABSR; // AB Select Status Register AT91_REG Reserved28[9]; // AT91_REG SYS_PIOB_OWER; // Output Write Enable Register AT91_REG SYS_PIOB_OWDR; // Output Write Disable Register AT91_REG SYS_PIOB_OWSR; // Output Write Status Register AT91_REG Reserved29[85]; // AT91_REG SYS_PIOC_PER; // PIO Enable Register AT91_REG SYS_PIOC_PDR; // PIO Disable Register AT91_REG SYS_PIOC_PSR; // PIO Status Register AT91_REG Reserved30[1]; // AT91_REG SYS_PIOC_OER; // Output Enable Register AT91_REG SYS_PIOC_ODR; // Output Disable Registerr AT91_REG SYS_PIOC_OSR; // Output Status Register AT91_REG Reserved31[1]; // AT91_REG SYS_PIOC_IFER; // Input Filter Enable Register AT91_REG SYS_PIOC_IFDR; // Input Filter Disable Register AT91_REG SYS_PIOC_IFSR; // Input Filter Status Register AT91_REG Reserved32[1]; // AT91_REG SYS_PIOC_SODR; // Set Output Data Register AT91_REG SYS_PIOC_CODR; // Clear Output Data Register AT91_REG SYS_PIOC_ODSR; // Output Data Status Register AT91_REG SYS_PIOC_PDSR; // Pin Data Status Register AT91_REG SYS_PIOC_IER; // Interrupt Enable Register AT91_REG SYS_PIOC_IDR; // Interrupt Disable Register AT91_REG SYS_PIOC_IMR; // Interrupt Mask Register AT91_REG SYS_PIOC_ISR; // Interrupt Status Register AT91_REG SYS_PIOC_MDER; // Multi-driver Enable Register AT91_REG SYS_PIOC_MDDR; // Multi-driver Disable Register AT91_REG SYS_PIOC_MDSR; // Multi-driver Status Register AT91_REG Reserved33[1]; // AT91_REG SYS_PIOC_PPUDR; // Pull-up Disable Register AT91_REG SYS_PIOC_PPUER; // Pull-up Enable Register AT91_REG SYS_PIOC_PPUSR; // Pull-up Status Register AT91_REG Reserved34[1]; // AT91_REG SYS_PIOC_ASR; // Select A Register AT91_REG SYS_PIOC_BSR; // Select B Register AT91_REG SYS_PIOC_ABSR; // AB Select Status Register AT91_REG Reserved35[9]; // AT91_REG SYS_PIOC_OWER; // Output Write Enable Register AT91_REG SYS_PIOC_OWDR; // Output Write Disable Register AT91_REG SYS_PIOC_OWSR; // Output Write Status Register AT91_REG Reserved36[85]; // AT91_REG SYS_PIOD_PER; // PIO Enable Register AT91_REG SYS_PIOD_PDR; // PIO Disable Register AT91_REG SYS_PIOD_PSR; // PIO Status Register AT91_REG Reserved37[1]; // AT91_REG SYS_PIOD_OER; // Output Enable Register AT91_REG SYS_PIOD_ODR; // Output Disable Registerr AT91_REG SYS_PIOD_OSR; // Output Status Register AT91_REG Reserved38[1]; // AT91_REG SYS_PIOD_IFER; // Input Filter Enable Register AT91_REG SYS_PIOD_IFDR; // Input Filter Disable Register AT91_REG SYS_PIOD_IFSR; // Input Filter Status Register AT91_REG Reserved39[1]; // AT91_REG SYS_PIOD_SODR; // Set Output Data Register AT91_REG SYS_PIOD_CODR; // Clear Output Data Register AT91_REG SYS_PIOD_ODSR; // Output Data Status Register AT91_REG SYS_PIOD_PDSR; // Pin Data Status Register AT91_REG SYS_PIOD_IER; // Interrupt Enable Register AT91_REG SYS_PIOD_IDR; // Interrupt Disable Register AT91_REG SYS_PIOD_IMR; // Interrupt Mask Register AT91_REG SYS_PIOD_ISR; // Interrupt Status Register AT91_REG SYS_PIOD_MDER; // Multi-driver Enable Register AT91_REG SYS_PIOD_MDDR; // Multi-driver Disable Register AT91_REG SYS_PIOD_MDSR; // Multi-driver Status Register AT91_REG Reserved40[1]; // AT91_REG SYS_PIOD_PPUDR; // Pull-up Disable Register AT91_REG SYS_PIOD_PPUER; // Pull-up Enable Register AT91_REG SYS_PIOD_PPUSR; // Pull-up Status Register AT91_REG Reserved41[1]; // AT91_REG SYS_PIOD_ASR; // Select A Register AT91_REG SYS_PIOD_BSR; // Select B Register AT91_REG SYS_PIOD_ABSR; // AB Select Status Register AT91_REG Reserved42[9]; // AT91_REG SYS_PIOD_OWER; // Output Write Enable Register AT91_REG SYS_PIOD_OWDR; // Output Write Disable Register AT91_REG SYS_PIOD_OWSR; // Output Write Status Register AT91_REG Reserved43[85]; // AT91_REG SYS_PIOE_PER; // PIO Enable Register AT91_REG SYS_PIOE_PDR; // PIO Disable Register AT91_REG SYS_PIOE_PSR; // PIO Status Register AT91_REG Reserved44[1]; // AT91_REG SYS_PIOE_OER; // Output Enable Register AT91_REG SYS_PIOE_ODR; // Output Disable Registerr AT91_REG SYS_PIOE_OSR; // Output Status Register AT91_REG Reserved45[1]; // AT91_REG SYS_PIOE_IFER; // Input Filter Enable Register AT91_REG SYS_PIOE_IFDR; // Input Filter Disable Register AT91_REG SYS_PIOE_IFSR; // Input Filter Status Register AT91_REG Reserved46[1]; // AT91_REG SYS_PIOE_SODR; // Set Output Data Register AT91_REG SYS_PIOE_CODR; // Clear Output Data Register AT91_REG SYS_PIOE_ODSR; // Output Data Status Register AT91_REG SYS_PIOE_PDSR; // Pin Data Status Register AT91_REG SYS_PIOE_IER; // Interrupt Enable Register AT91_REG SYS_PIOE_IDR; // Interrupt Disable Register AT91_REG SYS_PIOE_IMR; // Interrupt Mask Register AT91_REG SYS_PIOE_ISR; // Interrupt Status Register AT91_REG SYS_PIOE_MDER; // Multi-driver Enable Register AT91_REG SYS_PIOE_MDDR; // Multi-driver Disable Register AT91_REG SYS_PIOE_MDSR; // Multi-driver Status Register AT91_REG Reserved47[1]; // AT91_REG SYS_PIOE_PPUDR; // Pull-up Disable Register AT91_REG SYS_PIOE_PPUER; // Pull-up Enable Register AT91_REG SYS_PIOE_PPUSR; // Pull-up Status Register AT91_REG Reserved48[1]; // AT91_REG SYS_PIOE_ASR; // Select A Register AT91_REG SYS_PIOE_BSR; // Select B Register AT91_REG SYS_PIOE_ABSR; // AB Select Status Register AT91_REG Reserved49[9]; // AT91_REG SYS_PIOE_OWER; // Output Write Enable Register AT91_REG SYS_PIOE_OWDR; // Output Write Disable Register AT91_REG SYS_PIOE_OWSR; // Output Write Status Register AT91_REG Reserved50[85]; // AT91_REG SYS_PMC_SCER; // System Clock Enable Register AT91_REG SYS_PMC_SCDR; // System Clock Disable Register AT91_REG SYS_PMC_SCSR; // System Clock Status Register AT91_REG Reserved51[1]; // AT91_REG SYS_PMC_PCER; // Peripheral Clock Enable Register AT91_REG SYS_PMC_PCDR; // Peripheral Clock Disable Register AT91_REG SYS_PMC_PCSR; // Peripheral Clock Status Register AT91_REG Reserved52[1]; // AT91_REG SYS_PMC_MOR; // Main Oscillator Register AT91_REG SYS_PMC_MCFR; // Main Clock Frequency Register AT91_REG SYS_PMC_PLLAR; // PLL A Register AT91_REG SYS_PMC_PLLBR; // PLL B Register AT91_REG SYS_PMC_MCKR; // Master Clock Register AT91_REG Reserved53[3]; // AT91_REG SYS_PMC_PCKR[8]; // Programmable Clock Register AT91_REG SYS_PMC_IER; // Interrupt Enable Register AT91_REG SYS_PMC_IDR; // Interrupt Disable Register AT91_REG SYS_PMC_SR; // Status Register AT91_REG SYS_PMC_IMR; // Interrupt Mask Register AT91_REG Reserved54[36]; // AT91_REG SYS_RSTC_RCR; // Reset Control Register AT91_REG SYS_RSTC_RSR; // Reset Status Register AT91_REG SYS_RSTC_RMR; // Reset Mode Register AT91_REG Reserved55[1]; // AT91_REG SYS_SHDWC_SHCR; // Shut Down Control Register AT91_REG SYS_SHDWC_SHMR; // Shut Down Mode Register AT91_REG SYS_SHDWC_SHSR; // Shut Down Status Register AT91_REG Reserved56[1]; // AT91_REG SYS_RTTC0_RTMR; // Real-time Mode Register AT91_REG SYS_RTTC0_RTAR; // Real-time Alarm Register AT91_REG SYS_RTTC0_RTVR; // Real-time Value Register AT91_REG SYS_RTTC0_RTSR; // Real-time Status Register AT91_REG SYS_PITC_PIMR; // Period Interval Mode Register AT91_REG SYS_PITC_PISR; // Period Interval Status Register AT91_REG SYS_PITC_PIVR; // Period Interval Value Register AT91_REG SYS_PITC_PIIR; // Period Interval Image Register AT91_REG SYS_WDTC_WDCR; // Watchdog Control Register AT91_REG SYS_WDTC_WDMR; // Watchdog Mode Register AT91_REG SYS_WDTC_WDSR; // Watchdog Status Register AT91_REG Reserved57[1]; // AT91_REG SYS_RTTC1_RTMR; // Real-time Mode Register AT91_REG SYS_RTTC1_RTAR; // Real-time Alarm Register AT91_REG SYS_RTTC1_RTVR; // Real-time Value Register AT91_REG SYS_RTTC1_RTSR; // Real-time Status Register AT91_REG SYS_GPBR[20]; // General Purpose Register } AT91S_SYS, *AT91PS_SYS; #else #define ECC0 (AT91_CAST(AT91_REG *) 0x00000000) // (ECC0) ECC 0 #define ECC1 (AT91_CAST(AT91_REG *) 0x00000600) // (ECC1) ECC 0 #define GPBR (AT91_CAST(AT91_REG *) 0x00001D60) // (GPBR) General Purpose Register #endif // -------- GPBR : (SYS Offset: 0x1d60) GPBR General Purpose Register -------- #define AT91C_GPBR_GPRV (0x0 << 0) // (SYS) General Purpose Register Value // ***************************************************************************** // SOFTWARE API DEFINITION FOR External Bus Interface 0 // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_EBI0 { AT91_REG EBI0_DUMMY; // Dummy register - Do not use } AT91S_EBI0, *AT91PS_EBI0; #else #define EBI0_DUMMY (AT91_CAST(AT91_REG *) 0x00000000) // (EBI0_DUMMY) Dummy register - Do not use #endif // ***************************************************************************** // SOFTWARE API DEFINITION FOR SDRAM Controller Interface // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_SDRAMC { AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register } AT91S_SDRAMC, *AT91PS_SDRAMC; #else #define SDRAMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (SDRAMC_MR) SDRAM Controller Mode Register #define SDRAMC_TR (AT91_CAST(AT91_REG *) 0x00000004) // (SDRAMC_TR) SDRAM Controller Refresh Timer Register #define SDRAMC_CR (AT91_CAST(AT91_REG *) 0x00000008) // (SDRAMC_CR) SDRAM Controller Configuration Register #define SDRAMC_HSR (AT91_CAST(AT91_REG *) 0x0000000C) // (SDRAMC_HSR) SDRAM Controller High Speed Register #define SDRAMC_LPR (AT91_CAST(AT91_REG *) 0x00000010) // (SDRAMC_LPR) SDRAM Controller Low Power Register #define SDRAMC_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SDRAMC_IER) SDRAM Controller Interrupt Enable Register #define SDRAMC_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SDRAMC_IDR) SDRAM Controller Interrupt Disable Register #define SDRAMC_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SDRAMC_IMR) SDRAM Controller Interrupt Mask Register #define SDRAMC_ISR (AT91_CAST(AT91_REG *) 0x00000020) // (SDRAMC_ISR) SDRAM Controller Interrupt Mask Register #define SDRAMC_MDR (AT91_CAST(AT91_REG *) 0x00000024) // (SDRAMC_MDR) SDRAM Memory Device Register #endif // -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register -------- #define AT91C_SDRAMC_MODE (0xF << 0) // (SDRAMC) Mode #define AT91C_SDRAMC_MODE_NORMAL_CMD (0x0) // (SDRAMC) Normal Mode #define AT91C_SDRAMC_MODE_NOP_CMD (0x1) // (SDRAMC) Issue a NOP Command at every access #define AT91C_SDRAMC_MODE_PRCGALL_CMD (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access #define AT91C_SDRAMC_MODE_LMR_CMD (0x3) // (SDRAMC) Issue a Load Mode Register at every access #define AT91C_SDRAMC_MODE_RFSH_CMD (0x4) // (SDRAMC) Issue a Refresh #define AT91C_SDRAMC_MODE_EXT_LMR_CMD (0x5) // (SDRAMC) Issue an Extended Load Mode Register #define AT91C_SDRAMC_MODE_DEEP_CMD (0x6) // (SDRAMC) Enter Deep Power Mode // -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register -------- #define AT91C_SDRAMC_COUNT (0xFFF << 0) // (SDRAMC) Refresh Counter // -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register -------- #define AT91C_SDRAMC_NC (0x3 << 0) // (SDRAMC) Number of Column Bits #define AT91C_SDRAMC_NC_8 (0x0) // (SDRAMC) 8 Bits #define AT91C_SDRAMC_NC_9 (0x1) // (SDRAMC) 9 Bits #define AT91C_SDRAMC_NC_10 (0x2) // (SDRAMC) 10 Bits #define AT91C_SDRAMC_NC_11 (0x3) // (SDRAMC) 11 Bits #define AT91C_SDRAMC_NR (0x3 << 2) // (SDRAMC) Number of Row Bits #define AT91C_SDRAMC_NR_11 (0x0 << 2) // (SDRAMC) 11 Bits #define AT91C_SDRAMC_NR_12 (0x1 << 2) // (SDRAMC) 12 Bits #define AT91C_SDRAMC_NR_13 (0x2 << 2) // (SDRAMC) 13 Bits #define AT91C_SDRAMC_NB (0x1 << 4) // (SDRAMC) Number of Banks #define AT91C_SDRAMC_NB_2_BANKS (0x0 << 4) // (SDRAMC) 2 banks #define AT91C_SDRAMC_NB_4_BANKS (0x1 << 4) // (SDRAMC) 4 banks #define AT91C_SDRAMC_CAS (0x3 << 5) // (SDRAMC) CAS Latency #define AT91C_SDRAMC_CAS_2 (0x2 << 5) // (SDRAMC) 2 cycles #define AT91C_SDRAMC_CAS_3 (0x3 << 5) // (SDRAMC) 3 cycles #define AT91C_SDRAMC_DBW (0x1 << 7) // (SDRAMC) Data Bus Width #define AT91C_SDRAMC_DBW_32_BITS (0x0 << 7) // (SDRAMC) 32 Bits datas bus #define AT91C_SDRAMC_DBW_16_BITS (0x1 << 7) // (SDRAMC) 16 Bits datas bus #define AT91C_SDRAMC_TWR (0xF << 8) // (SDRAMC) Number of Write Recovery Time Cycles #define AT91C_SDRAMC_TWR_0 (0x0 << 8) // (SDRAMC) Value : 0 #define AT91C_SDRAMC_TWR_1 (0x1 << 8) // (SDRAMC) Value : 1 #define AT91C_SDRAMC_TWR_2 (0x2 << 8) // (SDRAMC) Value : 2 #define AT91C_SDRAMC_TWR_3 (0x3 << 8) // (SDRAMC) Value : 3 #define AT91C_SDRAMC_TWR_4 (0x4 << 8) // (SDRAMC) Value : 4 #define AT91C_SDRAMC_TWR_5 (0x5 << 8) // (SDRAMC) Value : 5 #define AT91C_SDRAMC_TWR_6 (0x6 << 8) // (SDRAMC) Value : 6 #define AT91C_SDRAMC_TWR_7 (0x7 << 8) // (SDRAMC) Value : 7 #define AT91C_SDRAMC_TWR_8 (0x8 << 8) // (SDRAMC) Value : 8 #define AT91C_SDRAMC_TWR_9 (0x9 << 8) // (SDRAMC) Value : 9 #define AT91C_SDRAMC_TWR_10 (0xA << 8) // (SDRAMC) Value : 10 #define AT91C_SDRAMC_TWR_11 (0xB << 8) // (SDRAMC) Value : 11 #define AT91C_SDRAMC_TWR_12 (0xC << 8) // (SDRAMC) Value : 12 #define AT91C_SDRAMC_TWR_13 (0xD << 8) // (SDRAMC) Value : 13 #define AT91C_SDRAMC_TWR_14 (0xE << 8) // (SDRAMC) Value : 14 #define AT91C_SDRAMC_TWR_15 (0xF << 8) // (SDRAMC) Value : 15 #define AT91C_SDRAMC_TRC (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles #define AT91C_SDRAMC_TRC_0 (0x0 << 12) // (SDRAMC) Value : 0 #define AT91C_SDRAMC_TRC_1 (0x1 << 12) // (SDRAMC) Value : 1 #define AT91C_SDRAMC_TRC_2 (0x2 << 12) // (SDRAMC) Value : 2 #define AT91C_SDRAMC_TRC_3 (0x3 << 12) // (SDRAMC) Value : 3 #define AT91C_SDRAMC_TRC_4 (0x4 << 12) // (SDRAMC) Value : 4 #define AT91C_SDRAMC_TRC_5 (0x5 << 12) // (SDRAMC) Value : 5 #define AT91C_SDRAMC_TRC_6 (0x6 << 12) // (SDRAMC) Value : 6 #define AT91C_SDRAMC_TRC_7 (0x7 << 12) // (SDRAMC) Value : 7 #define AT91C_SDRAMC_TRC_8 (0x8 << 12) // (SDRAMC) Value : 8 #define AT91C_SDRAMC_TRC_9 (0x9 << 12) // (SDRAMC) Value : 9 #define AT91C_SDRAMC_TRC_10 (0xA << 12) // (SDRAMC) Value : 10 #define AT91C_SDRAMC_TRC_11 (0xB << 12) // (SDRAMC) Value : 11 #define AT91C_SDRAMC_TRC_12 (0xC << 12) // (SDRAMC) Value : 12 #define AT91C_SDRAMC_TRC_13 (0xD << 12) // (SDRAMC) Value : 13 #define AT91C_SDRAMC_TRC_14 (0xE << 12) // (SDRAMC) Value : 14 #define AT91C_SDRAMC_TRC_15 (0xF << 12) // (SDRAMC) Value : 15 #define AT91C_SDRAMC_TRP (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles #define AT91C_SDRAMC_TRP_0 (0x0 << 16) // (SDRAMC) Value : 0 #define AT91C_SDRAMC_TRP_1 (0x1 << 16) // (SDRAMC) Value : 1 #define AT91C_SDRAMC_TRP_2 (0x2 << 16) // (SDRAMC) Value : 2 #define AT91C_SDRAMC_TRP_3 (0x3 << 16) // (SDRAMC) Value : 3 #define AT91C_SDRAMC_TRP_4 (0x4 << 16) // (SDRAMC) Value : 4 #define AT91C_SDRAMC_TRP_5 (0x5 << 16) // (SDRAMC) Value : 5 #define AT91C_SDRAMC_TRP_6 (0x6 << 16) // (SDRAMC) Value : 6 #define AT91C_SDRAMC_TRP_7 (0x7 << 16) // (SDRAMC) Value : 7 #define AT91C_SDRAMC_TRP_8 (0x8 << 16) // (SDRAMC) Value : 8 #define AT91C_SDRAMC_TRP_9 (0x9 << 16) // (SDRAMC) Value : 9 #define AT91C_SDRAMC_TRP_10 (0xA << 16) // (SDRAMC) Value : 10 #define AT91C_SDRAMC_TRP_11 (0xB << 16) // (SDRAMC) Value : 11 #define AT91C_SDRAMC_TRP_12 (0xC << 16) // (SDRAMC) Value : 12 #define AT91C_SDRAMC_TRP_13 (0xD << 16) // (SDRAMC) Value : 13 #define AT91C_SDRAMC_TRP_14 (0xE << 16) // (SDRAMC) Value : 14 #define AT91C_SDRAMC_TRP_15 (0xF << 16) // (SDRAMC) Value : 15 #define AT91C_SDRAMC_TRCD (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles #define AT91C_SDRAMC_TRCD_0 (0x0 << 20) // (SDRAMC) Value : 0 #define AT91C_SDRAMC_TRCD_1 (0x1 << 20) // (SDRAMC) Value : 1 #define AT91C_SDRAMC_TRCD_2 (0x2 << 20) // (SDRAMC) Value : 2 #define AT91C_SDRAMC_TRCD_3 (0x3 << 20) // (SDRAMC) Value : 3 #define AT91C_SDRAMC_TRCD_4 (0x4 << 20) // (SDRAMC) Value : 4 #define AT91C_SDRAMC_TRCD_5 (0x5 << 20) // (SDRAMC) Value : 5 #define AT91C_SDRAMC_TRCD_6 (0x6 << 20) // (SDRAMC) Value : 6 #define AT91C_SDRAMC_TRCD_7 (0x7 << 20) // (SDRAMC) Value : 7 #define AT91C_SDRAMC_TRCD_8 (0x8 << 20) // (SDRAMC) Value : 8 #define AT91C_SDRAMC_TRCD_9 (0x9 << 20) // (SDRAMC) Value : 9 #define AT91C_SDRAMC_TRCD_10 (0xA << 20) // (SDRAMC) Value : 10 #define AT91C_SDRAMC_TRCD_11 (0xB << 20) // (SDRAMC) Value : 11 #define AT91C_SDRAMC_TRCD_12 (0xC << 20) // (SDRAMC) Value : 12 #define AT91C_SDRAMC_TRCD_13 (0xD << 20) // (SDRAMC) Value : 13 #define AT91C_SDRAMC_TRCD_14 (0xE << 20) // (SDRAMC) Value : 14 #define AT91C_SDRAMC_TRCD_15 (0xF << 20) // (SDRAMC) Value : 15 #define AT91C_SDRAMC_TRAS (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles #define AT91C_SDRAMC_TRAS_0 (0x0 << 24) // (SDRAMC) Value : 0 #define AT91C_SDRAMC_TRAS_1 (0x1 << 24) // (SDRAMC) Value : 1 #define AT91C_SDRAMC_TRAS_2 (0x2 << 24) // (SDRAMC) Value : 2 #define AT91C_SDRAMC_TRAS_3 (0x3 << 24) // (SDRAMC) Value : 3 #define AT91C_SDRAMC_TRAS_4 (0x4 << 24) // (SDRAMC) Value : 4 #define AT91C_SDRAMC_TRAS_5 (0x5 << 24) // (SDRAMC) Value : 5 #define AT91C_SDRAMC_TRAS_6 (0x6 << 24) // (SDRAMC) Value : 6 #define AT91C_SDRAMC_TRAS_7 (0x7 << 24) // (SDRAMC) Value : 7 #define AT91C_SDRAMC_TRAS_8 (0x8 << 24) // (SDRAMC) Value : 8 #define AT91C_SDRAMC_TRAS_9 (0x9 << 24) // (SDRAMC) Value : 9 #define AT91C_SDRAMC_TRAS_10 (0xA << 24) // (SDRAMC) Value : 10 #define AT91C_SDRAMC_TRAS_11 (0xB << 24) // (SDRAMC) Value : 11 #define AT91C_SDRAMC_TRAS_12 (0xC << 24) // (SDRAMC) Value : 12 #define AT91C_SDRAMC_TRAS_13 (0xD << 24) // (SDRAMC) Value : 13 #define AT91C_SDRAMC_TRAS_14 (0xE << 24) // (SDRAMC) Value : 14 #define AT91C_SDRAMC_TRAS_15 (0xF << 24) // (SDRAMC) Value : 15 #define AT91C_SDRAMC_TXSR (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles #define AT91C_SDRAMC_TXSR_0 (0x0 << 28) // (SDRAMC) Value : 0 #define AT91C_SDRAMC_TXSR_1 (0x1 << 28) // (SDRAMC) Value : 1 #define AT91C_SDRAMC_TXSR_2 (0x2 << 28) // (SDRAMC) Value : 2 #define AT91C_SDRAMC_TXSR_3 (0x3 << 28) // (SDRAMC) Value : 3 #define AT91C_SDRAMC_TXSR_4 (0x4 << 28) // (SDRAMC) Value : 4 #define AT91C_SDRAMC_TXSR_5 (0x5 << 28) // (SDRAMC) Value : 5 #define AT91C_SDRAMC_TXSR_6 (0x6 << 28) // (SDRAMC) Value : 6 #define AT91C_SDRAMC_TXSR_7 (0x7 << 28) // (SDRAMC) Value : 7 #define AT91C_SDRAMC_TXSR_8 (0x8 << 28) // (SDRAMC) Value : 8 #define AT91C_SDRAMC_TXSR_9 (0x9 << 28) // (SDRAMC) Value : 9 #define AT91C_SDRAMC_TXSR_10 (0xA << 28) // (SDRAMC) Value : 10 #define AT91C_SDRAMC_TXSR_11 (0xB << 28) // (SDRAMC) Value : 11 #define AT91C_SDRAMC_TXSR_12 (0xC << 28) // (SDRAMC) Value : 12 #define AT91C_SDRAMC_TXSR_13 (0xD << 28) // (SDRAMC) Value : 13 #define AT91C_SDRAMC_TXSR_14 (0xE << 28) // (SDRAMC) Value : 14 #define AT91C_SDRAMC_TXSR_15 (0xF << 28) // (SDRAMC) Value : 15 // -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register -------- #define AT91C_SDRAMC_DA (0x1 << 0) // (SDRAMC) Decode Cycle Enable Bit #define AT91C_SDRAMC_DA_DISABLE (0x0) // (SDRAMC) Disable Decode Cycle #define AT91C_SDRAMC_DA_ENABLE (0x1) // (SDRAMC) Enable Decode Cycle // -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register -------- #define AT91C_SDRAMC_LPCB (0x3 << 0) // (SDRAMC) Low-power Configurations #define AT91C_SDRAMC_LPCB_DISABLE (0x0) // (SDRAMC) Disable Low Power Features #define AT91C_SDRAMC_LPCB_SELF_REFRESH (0x1) // (SDRAMC) Enable SELF_REFRESH #define AT91C_SDRAMC_LPCB_POWER_DOWN (0x2) // (SDRAMC) Enable POWER_DOWN #define AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN #define AT91C_SDRAMC_PASR (0x7 << 4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM) #define AT91C_SDRAMC_TCSR (0x3 << 8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM) #define AT91C_SDRAMC_DS (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM) #define AT91C_SDRAMC_TIMEOUT (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled #define AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately #define AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer #define AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer // -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- #define AT91C_SDRAMC_RES (0x1 << 0) // (SDRAMC) Refresh Error Status // -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- // -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- // -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- // -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register -------- #define AT91C_SDRAMC_MD (0x3 << 0) // (SDRAMC) Memory Device Type #define AT91C_SDRAMC_MD_SDRAM (0x0) // (SDRAMC) SDRAM Mode #define AT91C_SDRAMC_MD_LOW_POWER_SDRAM (0x1) // (SDRAMC) SDRAM Low Power Mode // ***************************************************************************** // SOFTWARE API DEFINITION FOR Static Memory Controller Interface // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_SMC { AT91_REG SMC_SETUP0; // Setup Register for CS 0 AT91_REG SMC_PULSE0; // Pulse Register for CS 0 AT91_REG SMC_CYCLE0; // Cycle Register for CS 0 AT91_REG SMC_CTRL0; // Control Register for CS 0 AT91_REG SMC_SETUP1; // Setup Register for CS 1 AT91_REG SMC_PULSE1; // Pulse Register for CS 1 AT91_REG SMC_CYCLE1; // Cycle Register for CS 1 AT91_REG SMC_CTRL1; // Control Register for CS 1 AT91_REG SMC_SETUP2; // Setup Register for CS 2 AT91_REG SMC_PULSE2; // Pulse Register for CS 2 AT91_REG SMC_CYCLE2; // Cycle Register for CS 2 AT91_REG SMC_CTRL2; // Control Register for CS 2 AT91_REG SMC_SETUP3; // Setup Register for CS 3 AT91_REG SMC_PULSE3; // Pulse Register for CS 3 AT91_REG SMC_CYCLE3; // Cycle Register for CS 3 AT91_REG SMC_CTRL3; // Control Register for CS 3 AT91_REG SMC_SETUP4; // Setup Register for CS 4 AT91_REG SMC_PULSE4; // Pulse Register for CS 4 AT91_REG SMC_CYCLE4; // Cycle Register for CS 4 AT91_REG SMC_CTRL4; // Control Register for CS 4 AT91_REG SMC_SETUP5; // Setup Register for CS 5 AT91_REG SMC_PULSE5; // Pulse Register for CS 5 AT91_REG SMC_CYCLE5; // Cycle Register for CS 5 AT91_REG SMC_CTRL5; // Control Register for CS 5 AT91_REG SMC_SETUP6; // Setup Register for CS 6 AT91_REG SMC_PULSE6; // Pulse Register for CS 6 AT91_REG SMC_CYCLE6; // Cycle Register for CS 6 AT91_REG SMC_CTRL6; // Control Register for CS 6 AT91_REG SMC_SETUP7; // Setup Register for CS 7 AT91_REG SMC_PULSE7; // Pulse Register for CS 7 AT91_REG SMC_CYCLE7; // Cycle Register for CS 7 AT91_REG SMC_CTRL7; // Control Register for CS 7 } AT91S_SMC, *AT91PS_SMC; #else #define SETUP0 (AT91_CAST(AT91_REG *) 0x00000000) // (SETUP0) Setup Register for CS 0 #define PULSE0 (AT91_CAST(AT91_REG *) 0x00000004) // (PULSE0) Pulse Register for CS 0 #define CYCLE0 (AT91_CAST(AT91_REG *) 0x00000008) // (CYCLE0) Cycle Register for CS 0 #define CTRL0 (AT91_CAST(AT91_REG *) 0x0000000C) // (CTRL0) Control Register for CS 0 #define SETUP1 (AT91_CAST(AT91_REG *) 0x00000010) // (SETUP1) Setup Register for CS 1 #define PULSE1 (AT91_CAST(AT91_REG *) 0x00000014) // (PULSE1) Pulse Register for CS 1 #define CYCLE1 (AT91_CAST(AT91_REG *) 0x00000018) // (CYCLE1) Cycle Register for CS 1 #define CTRL1 (AT91_CAST(AT91_REG *) 0x0000001C) // (CTRL1) Control Register for CS 1 #define SETUP2 (AT91_CAST(AT91_REG *) 0x00000020) // (SETUP2) Setup Register for CS 2 #define PULSE2 (AT91_CAST(AT91_REG *) 0x00000024) // (PULSE2) Pulse Register for CS 2 #define CYCLE2 (AT91_CAST(AT91_REG *) 0x00000028) // (CYCLE2) Cycle Register for CS 2 #define CTRL2 (AT91_CAST(AT91_REG *) 0x0000002C) // (CTRL2) Control Register for CS 2 #define SETUP3 (AT91_CAST(AT91_REG *) 0x00000030) // (SETUP3) Setup Register for CS 3 #define PULSE3 (AT91_CAST(AT91_REG *) 0x00000034) // (PULSE3) Pulse Register for CS 3 #define CYCLE3 (AT91_CAST(AT91_REG *) 0x00000038) // (CYCLE3) Cycle Register for CS 3 #define CTRL3 (AT91_CAST(AT91_REG *) 0x0000003C) // (CTRL3) Control Register for CS 3 #define SETUP4 (AT91_CAST(AT91_REG *) 0x00000040) // (SETUP4) Setup Register for CS 4 #define PULSE4 (AT91_CAST(AT91_REG *) 0x00000044) // (PULSE4) Pulse Register for CS 4 #define CYCLE4 (AT91_CAST(AT91_REG *) 0x00000048) // (CYCLE4) Cycle Register for CS 4 #define CTRL4 (AT91_CAST(AT91_REG *) 0x0000004C) // (CTRL4) Control Register for CS 4 #define SETUP5 (AT91_CAST(AT91_REG *) 0x00000050) // (SETUP5) Setup Register for CS 5 #define PULSE5 (AT91_CAST(AT91_REG *) 0x00000054) // (PULSE5) Pulse Register for CS 5 #define CYCLE5 (AT91_CAST(AT91_REG *) 0x00000058) // (CYCLE5) Cycle Register for CS 5 #define CTRL5 (AT91_CAST(AT91_REG *) 0x0000005C) // (CTRL5) Control Register for CS 5 #define SETUP6 (AT91_CAST(AT91_REG *) 0x00000060) // (SETUP6) Setup Register for CS 6 #define PULSE6 (AT91_CAST(AT91_REG *) 0x00000064) // (PULSE6) Pulse Register for CS 6 #define CYCLE6 (AT91_CAST(AT91_REG *) 0x00000068) // (CYCLE6) Cycle Register for CS 6 #define CTRL6 (AT91_CAST(AT91_REG *) 0x0000006C) // (CTRL6) Control Register for CS 6 #define SETUP7 (AT91_CAST(AT91_REG *) 0x00000070) // (SETUP7) Setup Register for CS 7 #define PULSE7 (AT91_CAST(AT91_REG *) 0x00000074) // (PULSE7) Pulse Register for CS 7 #define CYCLE7 (AT91_CAST(AT91_REG *) 0x00000078) // (CYCLE7) Cycle Register for CS 7 #define CTRL7 (AT91_CAST(AT91_REG *) 0x0000007C) // (CTRL7) Control Register for CS 7 #endif // -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x -------- #define AT91C_SMC_NWESETUP (0x3F << 0) // (SMC) NWE Setup Length #define AT91C_SMC_NCSSETUPWR (0x3F << 8) // (SMC) NCS Setup Length in WRite Access #define AT91C_SMC_NRDSETUP (0x3F << 16) // (SMC) NRD Setup Length #define AT91C_SMC_NCSSETUPRD (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access // -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x -------- #define AT91C_SMC_NWEPULSE (0x7F << 0) // (SMC) NWE Pulse Length #define AT91C_SMC_NCSPULSEWR (0x7F << 8) // (SMC) NCS Pulse Length in WRite Access #define AT91C_SMC_NRDPULSE (0x7F << 16) // (SMC) NRD Pulse Length #define AT91C_SMC_NCSPULSERD (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access // -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x -------- #define AT91C_SMC_NWECYCLE (0x1FF << 0) // (SMC) Total Write Cycle Length #define AT91C_SMC_NRDCYCLE (0x1FF << 16) // (SMC) Total Read Cycle Length // -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x -------- #define AT91C_SMC_READMODE (0x1 << 0) // (SMC) Read Mode #define AT91C_SMC_WRITEMODE (0x1 << 1) // (SMC) Write Mode #define AT91C_SMC_NWAITM (0x3 << 5) // (SMC) NWAIT Mode #define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 5) // (SMC) External NWAIT disabled. #define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 5) // (SMC) External NWAIT enabled in frozen mode. #define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 5) // (SMC) External NWAIT enabled in ready mode. #define AT91C_SMC_BAT (0x1 << 8) // (SMC) Byte Access Type #define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. #define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. #define AT91C_SMC_DBW (0x3 << 12) // (SMC) Data Bus Width #define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) // (SMC) 8 bits. #define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) // (SMC) 16 bits. #define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits. #define AT91C_SMC_TDF (0xF << 16) // (SMC) Data Float Time. #define AT91C_SMC_TDFEN (0x1 << 20) // (SMC) TDF Enabled. #define AT91C_SMC_PMEN (0x1 << 24) // (SMC) Page Mode Enabled. #define AT91C_SMC_PS (0x3 << 28) // (SMC) Page Size #define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) // (SMC) 4 bytes. #define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) // (SMC) 8 bytes. #define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) // (SMC) 16 bytes. #define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes. // -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR External Bus Interface 1 // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_EBI1 { AT91_REG EBI1_DUMMY; // Dummy register - Do not use } AT91S_EBI1, *AT91PS_EBI1; #else #define EBI1_DUMMY (AT91_CAST(AT91_REG *) 0x00000000) // (EBI1_DUMMY) Dummy register - Do not use #endif // ***************************************************************************** // SOFTWARE API DEFINITION FOR AHB Matrix Interface // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_MATRIX { AT91_REG MATRIX_MCFG0; // Master Configuration Register 0 AT91_REG MATRIX_MCFG1; // Master Configuration Register 1 AT91_REG MATRIX_MCFG2; // Master Configuration Register 2 AT91_REG MATRIX_MCFG3; // Master Configuration Register 3 AT91_REG MATRIX_MCFG4; // Master Configuration Register 4 AT91_REG MATRIX_MCFG5; // Master Configuration Register 5 AT91_REG MATRIX_MCFG6; // Master Configuration Register 6 AT91_REG MATRIX_MCFG7; // Master Configuration Register 7 AT91_REG MATRIX_MCFG8; // Master Configuration Register 8 AT91_REG Reserved0[7]; // AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 AT91_REG MATRIX_SCFG5; // Slave Configuration Register 5 AT91_REG MATRIX_SCFG6; // Slave Configuration Register 6 AT91_REG MATRIX_SCFG7; // Slave Configuration Register 7 AT91_REG Reserved1[8]; // AT91_REG MATRIX_PRAS0; // PRAS0 AT91_REG MATRIX_PRBS0; // PRBS0 AT91_REG MATRIX_PRAS1; // PRAS1 AT91_REG MATRIX_PRBS1; // PRBS1 AT91_REG MATRIX_PRAS2; // PRAS2 AT91_REG MATRIX_PRBS2; // PRBS2 AT91_REG MATRIX_PRAS3; // PRAS3 AT91_REG MATRIX_PRBS3; // PRBS3 AT91_REG MATRIX_PRAS4; // PRAS4 AT91_REG MATRIX_PRBS4; // PRBS4 AT91_REG MATRIX_PRAS5; // PRAS5 AT91_REG MATRIX_PRBS5; // PRBS5 AT91_REG MATRIX_PRAS6; // PRAS6 AT91_REG MATRIX_PRBS6; // PRBS6 AT91_REG MATRIX_PRAS7; // PRAS7 AT91_REG MATRIX_PRBS7; // PRBS7 AT91_REG Reserved2[16]; // AT91_REG MATRIX_MRCR; // Master Remp Control Register } AT91S_MATRIX, *AT91PS_MATRIX; #else #define MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0x00000000) // (MATRIX_MCFG0) Master Configuration Register 0 #define MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0x00000004) // (MATRIX_MCFG1) Master Configuration Register 1 #define MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0x00000008) // (MATRIX_MCFG2) Master Configuration Register 2 #define MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0x0000000C) // (MATRIX_MCFG3) Master Configuration Register 3 #define MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0x00000010) // (MATRIX_MCFG4) Master Configuration Register 4 #define MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0x00000014) // (MATRIX_MCFG5) Master Configuration Register 5 #define MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0x00000018) // (MATRIX_MCFG6) Master Configuration Register 6 #define MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0x0000001C) // (MATRIX_MCFG7) Master Configuration Register 7 #define MATRIX_MCFG8 (AT91_CAST(AT91_REG *) 0x00000020) // (MATRIX_MCFG8) Master Configuration Register 8 #define MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0x00000040) // (MATRIX_SCFG0) Slave Configuration Register 0 #define MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0x00000044) // (MATRIX_SCFG1) Slave Configuration Register 1 #define MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0x00000048) // (MATRIX_SCFG2) Slave Configuration Register 2 #define MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0x0000004C) // (MATRIX_SCFG3) Slave Configuration Register 3 #define MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0x00000050) // (MATRIX_SCFG4) Slave Configuration Register 4 #define MATRIX_SCFG5 (AT91_CAST(AT91_REG *) 0x00000054) // (MATRIX_SCFG5) Slave Configuration Register 5 #define MATRIX_SCFG6 (AT91_CAST(AT91_REG *) 0x00000058) // (MATRIX_SCFG6) Slave Configuration Register 6 #define MATRIX_SCFG7 (AT91_CAST(AT91_REG *) 0x0000005C) // (MATRIX_SCFG7) Slave Configuration Register 7 #define MATRIX_PRAS0 (AT91_CAST(AT91_REG *) 0x00000080) // (MATRIX_PRAS0) PRAS0 #define MATRIX_PRBS0 (AT91_CAST(AT91_REG *) 0x00000084) // (MATRIX_PRBS0) PRBS0 #define MATRIX_PRAS1 (AT91_CAST(AT91_REG *) 0x00000088) // (MATRIX_PRAS1) PRAS1 #define MATRIX_PRBS1 (AT91_CAST(AT91_REG *) 0x0000008C) // (MATRIX_PRBS1) PRBS1 #define MATRIX_PRAS2 (AT91_CAST(AT91_REG *) 0x00000090) // (MATRIX_PRAS2) PRAS2 #define MATRIX_PRBS2 (AT91_CAST(AT91_REG *) 0x00000094) // (MATRIX_PRBS2) PRBS2 #define MATRIX_PRAS3 (AT91_CAST(AT91_REG *) 0x00000098) // (MATRIX_PRAS3) PRAS3 #define MATRIX_PRBS3 (AT91_CAST(AT91_REG *) 0x0000009C) // (MATRIX_PRBS3) PRBS3 #define MATRIX_PRAS4 (AT91_CAST(AT91_REG *) 0x000000A0) // (MATRIX_PRAS4) PRAS4 #define MATRIX_PRBS4 (AT91_CAST(AT91_REG *) 0x000000A4) // (MATRIX_PRBS4) PRBS4 #define MATRIX_PRAS5 (AT91_CAST(AT91_REG *) 0x000000A8) // (MATRIX_PRAS5) PRAS5 #define MATRIX_PRBS5 (AT91_CAST(AT91_REG *) 0x000000AC) // (MATRIX_PRBS5) PRBS5 #define MATRIX_PRAS6 (AT91_CAST(AT91_REG *) 0x000000B0) // (MATRIX_PRAS6) PRAS6 #define MATRIX_PRBS6 (AT91_CAST(AT91_REG *) 0x000000B4) // (MATRIX_PRBS6) PRBS6 #define MATRIX_PRAS7 (AT91_CAST(AT91_REG *) 0x000000B8) // (MATRIX_PRAS7) PRAS7 #define MATRIX_PRBS7 (AT91_CAST(AT91_REG *) 0x000000BC) // (MATRIX_PRBS7) PRBS7 #define MATRIX_MRCR (AT91_CAST(AT91_REG *) 0x00000100) // (MATRIX_MRCR) Master Remp Control Register #endif // -------- MATRIX_MCFG0 : (MATRIX Offset: 0x0) Master Configuration Register rom -------- #define AT91C_MATRIX_ULBT (0x7 << 0) // (MATRIX) Undefined Length Burst Type // -------- MATRIX_MCFG1 : (MATRIX Offset: 0x4) Master Configuration Register htcm -------- // -------- MATRIX_MCFG2 : (MATRIX Offset: 0x8) Master Configuration Register gps_tcm -------- // -------- MATRIX_MCFG3 : (MATRIX Offset: 0xc) Master Configuration Register hperiphs -------- // -------- MATRIX_MCFG4 : (MATRIX Offset: 0x10) Master Configuration Register ebi0 -------- // -------- MATRIX_MCFG5 : (MATRIX Offset: 0x14) Master Configuration Register ebi1 -------- // -------- MATRIX_MCFG6 : (MATRIX Offset: 0x18) Master Configuration Register bridge -------- // -------- MATRIX_MCFG7 : (MATRIX Offset: 0x1c) Master Configuration Register gps -------- // -------- MATRIX_MCFG8 : (MATRIX Offset: 0x20) Master Configuration Register gps -------- // -------- MATRIX_SCFG0 : (MATRIX Offset: 0x40) Slave Configuration Register 0 -------- #define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst #define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type #define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. #define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. #define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. #define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master #define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR0_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR0_2DGC (0x4 << 18) // (MATRIX) 2DGC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR0_ISI (0x5 << 18) // (MATRIX) ISI Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR0_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR0_EMAC (0x7 << 18) // (MATRIX) EMAC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR0_USB (0x8 << 18) // (MATRIX) USB Master is Default Master #define AT91C_MATRIX_ARBT (0x3 << 24) // (MATRIX) Arbitration Type // -------- MATRIX_SCFG1 : (MATRIX Offset: 0x44) Slave Configuration Register 1 -------- #define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master #define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR1_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR1_2DGC (0x4 << 18) // (MATRIX) 2DGC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR1_ISI (0x5 << 18) // (MATRIX) ISI Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR1_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR1_EMAC (0x7 << 18) // (MATRIX) EMAC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR1_USB (0x8 << 18) // (MATRIX) USB Master is Default Master // -------- MATRIX_SCFG2 : (MATRIX Offset: 0x48) Slave Configuration Register 2 -------- #define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master #define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR2_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master // -------- MATRIX_SCFG3 : (MATRIX Offset: 0x4c) Slave Configuration Register 3 -------- #define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master #define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR3_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR3_2DGC (0x4 << 18) // (MATRIX) 2DGC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR3_ISI (0x5 << 18) // (MATRIX) ISI Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR3_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR3_EMAC (0x7 << 18) // (MATRIX) EMAC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR3_USB (0x8 << 18) // (MATRIX) USB Master is Default Master // -------- MATRIX_SCFG4 : (MATRIX Offset: 0x50) Slave Configuration Register 4 -------- #define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master #define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR4_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master // -------- MATRIX_SCFG5 : (MATRIX Offset: 0x54) Slave Configuration Register 5 -------- #define AT91C_MATRIX_FIXED_DEFMSTR5 (0x3 << 18) // (MATRIX) Fixed Index of Default Master #define AT91C_MATRIX_FIXED_DEFMSTR5_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR5_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR5_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR5_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR5_2DGC (0x4 << 18) // (MATRIX) 2DGC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR5_ISI (0x5 << 18) // (MATRIX) ISI Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR5_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR5_EMAC (0x7 << 18) // (MATRIX) EMAC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR5_USB (0x8 << 18) // (MATRIX) USB Master is Default Master // -------- MATRIX_SCFG6 : (MATRIX Offset: 0x58) Slave Configuration Register 6 -------- #define AT91C_MATRIX_FIXED_DEFMSTR6 (0x3 << 18) // (MATRIX) Fixed Index of Default Master #define AT91C_MATRIX_FIXED_DEFMSTR6_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR6_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR6_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR6_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR6_2DGC (0x4 << 18) // (MATRIX) 2DGC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR6_ISI (0x5 << 18) // (MATRIX) ISI Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR6_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR6_EMAC (0x7 << 18) // (MATRIX) EMAC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR6_USB (0x8 << 18) // (MATRIX) USB Master is Default Master // -------- MATRIX_SCFG7 : (MATRIX Offset: 0x5c) Slave Configuration Register 7 -------- #define AT91C_MATRIX_FIXED_DEFMSTR7 (0x3 << 18) // (MATRIX) Fixed Index of Default Master #define AT91C_MATRIX_FIXED_DEFMSTR7_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR7_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR7_PDC (0x2 << 18) // (MATRIX) PDC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR7_DMA (0x6 << 18) // (MATRIX) DMA Controller Master is Default Master // -------- MATRIX_PRAS0 : (MATRIX Offset: 0x80) PRAS0 Register -------- #define AT91C_MATRIX_M0PR (0x3 << 0) // (MATRIX) ARM926EJ-S Instruction priority #define AT91C_MATRIX_M1PR (0x3 << 4) // (MATRIX) ARM926EJ-S Data priority #define AT91C_MATRIX_M2PR (0x3 << 8) // (MATRIX) PDC priority #define AT91C_MATRIX_M3PR (0x3 << 12) // (MATRIX) LCDC priority #define AT91C_MATRIX_M4PR (0x3 << 16) // (MATRIX) 2DGC priority #define AT91C_MATRIX_M5PR (0x3 << 20) // (MATRIX) ISI priority #define AT91C_MATRIX_M6PR (0x3 << 24) // (MATRIX) DMA priority #define AT91C_MATRIX_M7PR (0x3 << 28) // (MATRIX) EMAC priority // -------- MATRIX_PRBS0 : (MATRIX Offset: 0x84) PRBS0 Register -------- #define AT91C_MATRIX_M8PR (0x3 << 0) // (MATRIX) USB priority // -------- MATRIX_PRAS1 : (MATRIX Offset: 0x88) PRAS1 Register -------- // -------- MATRIX_PRBS1 : (MATRIX Offset: 0x8c) PRBS1 Register -------- // -------- MATRIX_PRAS2 : (MATRIX Offset: 0x90) PRAS2 Register -------- // -------- MATRIX_PRBS2 : (MATRIX Offset: 0x94) PRBS2 Register -------- // -------- MATRIX_PRAS3 : (MATRIX Offset: 0x98) PRAS3 Register -------- // -------- MATRIX_PRBS3 : (MATRIX Offset: 0x9c) PRBS3 Register -------- // -------- MATRIX_PRAS4 : (MATRIX Offset: 0xa0) PRAS4 Register -------- // -------- MATRIX_PRBS4 : (MATRIX Offset: 0xa4) PRBS4 Register -------- // -------- MATRIX_PRAS5 : (MATRIX Offset: 0xa8) PRAS5 Register -------- // -------- MATRIX_PRBS5 : (MATRIX Offset: 0xac) PRBS5 Register -------- // -------- MATRIX_PRAS6 : (MATRIX Offset: 0xb0) PRAS6 Register -------- // -------- MATRIX_PRBS6 : (MATRIX Offset: 0xb4) PRBS6 Register -------- // -------- MATRIX_PRAS7 : (MATRIX Offset: 0xb8) PRAS7 Register -------- // -------- MATRIX_PRBS7 : (MATRIX Offset: 0xbc) PRBS7 Register -------- // -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register -------- #define AT91C_MATRIX_RCA926I (0x1 << 0) // (MATRIX) Remap Command Bit for ARM926EJ-S Instruction #define AT91C_MATRIX_RCA926D (0x1 << 1) // (MATRIX) Remap Command Bit for ARM926EJ-S Data #define AT91C_MATRIX_RCB2 (0x1 << 2) // (MATRIX) Remap Command Bit for PDC #define AT91C_MATRIX_RCB3 (0x1 << 3) // (MATRIX) Remap Command Bit for LCD #define AT91C_MATRIX_RCB4 (0x1 << 4) // (MATRIX) Remap Command Bit for 2DGC #define AT91C_MATRIX_RCB5 (0x1 << 5) // (MATRIX) Remap Command Bit for ISI #define AT91C_MATRIX_RCB6 (0x1 << 6) // (MATRIX) Remap Command Bit for DMA #define AT91C_MATRIX_RCB7 (0x1 << 7) // (MATRIX) Remap Command Bit for EMAC #define AT91C_MATRIX_RCB8 (0x1 << 8) // (MATRIX) Remap Command Bit for USB // ***************************************************************************** // SOFTWARE API DEFINITION FOR AHB CCFG Interface // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_CCFG { AT91_REG Reserved0[1]; // AT91_REG CCFG_TCMR; // TCM configuration AT91_REG Reserved1[2]; // AT91_REG CCFG_EBI0CSA; // EBI0 Chip Select Assignement Register AT91_REG CCFG_EBI1CSA; // EBI1 Chip Select Assignement Register AT91_REG Reserved2[53]; // AT91_REG CCFG_MATRIXVERSION; // Version Register } AT91S_CCFG, *AT91PS_CCFG; #else #define CCFG_TCMR (AT91_CAST(AT91_REG *) 0x00000004) // (CCFG_TCMR) TCM configuration #define CCFG_EBI0CSA (AT91_CAST(AT91_REG *) 0x00000010) // (CCFG_EBI0CSA) EBI0 Chip Select Assignement Register #define CCFG_EBI1CSA (AT91_CAST(AT91_REG *) 0x00000014) // (CCFG_EBI1CSA) EBI1 Chip Select Assignement Register #define CCFG_MATRIXVERSION (AT91_CAST(AT91_REG *) 0x000000EC) // (CCFG_MATRIXVERSION) Version Register #endif // -------- CCFG_TCMR : (CCFG Offset: 0x4) TCM Configuration -------- #define AT91C_CCFG_ITCM_SIZE (0xF << 0) // (CCFG) Size of ITCM enabled memory block #define AT91C_CCFG_ITCM_SIZE_0KB (0x0) // (CCFG) 0 KB (No ITCM Memory) #define AT91C_CCFG_ITCM_SIZE_16KB (0x5) // (CCFG) 16 KB #define AT91C_CCFG_ITCM_SIZE_32KB (0x6) // (CCFG) 32 KB #define AT91C_CCFG_DTCM_SIZE (0xF << 4) // (CCFG) Size of DTCM enabled memory block #define AT91C_CCFG_DTCM_SIZE_0KB (0x0 << 4) // (CCFG) 0 KB (No DTCM Memory) #define AT91C_CCFG_DTCM_SIZE_16KB (0x5 << 4) // (CCFG) 16 KB #define AT91C_CCFG_DTCM_SIZE_32KB (0x6 << 4) // (CCFG) 32 KB #define AT91C_CCFG_RM (0xF << 8) // (CCFG) Read Margin registers // -------- CCFG_EBI0CSA : (CCFG Offset: 0x10) EBI0 Chip Select Assignment Register -------- #define AT91C_EBI_CS1A (0x1 << 1) // (CCFG) Chip Select 1 Assignment #define AT91C_EBI_CS1A_SMC (0x0 << 1) // (CCFG) Chip Select 1 is assigned to the Static Memory Controller. #define AT91C_EBI_CS1A_SDRAMC (0x1 << 1) // (CCFG) Chip Select 1 is assigned to the SDRAM Controller. #define AT91C_EBI_CS3A (0x1 << 3) // (CCFG) Chip Select 3 Assignment #define AT91C_EBI_CS3A_SMC (0x0 << 3) // (CCFG) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC. #define AT91C_EBI_CS3A_SM (0x1 << 3) // (CCFG) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. #define AT91C_EBI_CS4A (0x1 << 4) // (CCFG) Chip Select 4 Assignment #define AT91C_EBI_CS4A_SMC (0x0 << 4) // (CCFG) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC. #define AT91C_EBI_CS4A_CF (0x1 << 4) // (CCFG) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated. #define AT91C_EBI_CS5A (0x1 << 5) // (CCFG) Chip Select 5 Assignment #define AT91C_EBI_CS5A_SMC (0x0 << 5) // (CCFG) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC #define AT91C_EBI_CS5A_CF (0x1 << 5) // (CCFG) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated. #define AT91C_EBI_DBPUC (0x1 << 8) // (CCFG) Data Bus Pull-up Configuration // -------- CCFG_EBI1CSA : (CCFG Offset: 0x14) EBI1 Chip Select Assignement Register -------- #define AT91C_EBI_CS2A (0x1 << 3) // (CCFG) EBI1 Chip Select 2 Assignment #define AT91C_EBI_CS2A_SMC (0x0 << 3) // (CCFG) Chip Select 2 is assigned to the Static Memory Controller. #define AT91C_EBI_CS2A_SM (0x1 << 3) // (CCFG) Chip Select 2 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. // ***************************************************************************** // SOFTWARE API DEFINITION FOR Peripheral DMA Controller // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_PDC { AT91_REG PDC_RPR; // Receive Pointer Register AT91_REG PDC_RCR; // Receive Counter Register AT91_REG PDC_TPR; // Transmit Pointer Register AT91_REG PDC_TCR; // Transmit Counter Register AT91_REG PDC_RNPR; // Receive Next Pointer Register AT91_REG PDC_RNCR; // Receive Next Counter Register AT91_REG PDC_TNPR; // Transmit Next Pointer Register AT91_REG PDC_TNCR; // Transmit Next Counter Register AT91_REG PDC_PTCR; // PDC Transfer Control Register AT91_REG PDC_PTSR; // PDC Transfer Status Register } AT91S_PDC, *AT91PS_PDC; #else #define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register #define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register #define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register #define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register #define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register #define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register #define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register #define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register #define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register #define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register #endif // -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- #define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable #define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable #define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable #define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable // -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Debug Unit // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_DBGU { AT91_REG DBGU_CR; // Control Register AT91_REG DBGU_MR; // Mode Register AT91_REG DBGU_IER; // Interrupt Enable Register AT91_REG DBGU_IDR; // Interrupt Disable Register AT91_REG DBGU_IMR; // Interrupt Mask Register AT91_REG DBGU_CSR; // Channel Status Register AT91_REG DBGU_RHR; // Receiver Holding Register AT91_REG DBGU_THR; // Transmitter Holding Register AT91_REG DBGU_BRGR; // Baud Rate Generator Register AT91_REG Reserved0[7]; // AT91_REG DBGU_CIDR; // Chip ID Register AT91_REG DBGU_EXID; // Chip ID Extension Register AT91_REG DBGU_FNTR; // Force NTRST Register AT91_REG Reserved1[45]; // AT91_REG DBGU_RPR; // Receive Pointer Register AT91_REG DBGU_RCR; // Receive Counter Register AT91_REG DBGU_TPR; // Transmit Pointer Register AT91_REG DBGU_TCR; // Transmit Counter Register AT91_REG DBGU_RNPR; // Receive Next Pointer Register AT91_REG DBGU_RNCR; // Receive Next Counter Register AT91_REG DBGU_TNPR; // Transmit Next Pointer Register AT91_REG DBGU_TNCR; // Transmit Next Counter Register AT91_REG DBGU_PTCR; // PDC Transfer Control Register AT91_REG DBGU_PTSR; // PDC Transfer Status Register } AT91S_DBGU, *AT91PS_DBGU; #else #define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register #define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register #define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register #define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register #define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register #define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register #define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register #define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register #define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register #define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register #define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register #define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register #endif // -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- #define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver #define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter #define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable #define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable #define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable #define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable #define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits // -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- #define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type #define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity #define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity #define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) #define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) #define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity #define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode #define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode #define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. #define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. #define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. #define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. // -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- #define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt #define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt #define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt #define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt #define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt #define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt #define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt #define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt #define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt #define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt #define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt #define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt // -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- #define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG // ***************************************************************************** // SOFTWARE API DEFINITION FOR Advanced Interrupt Controller // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_AIC { AT91_REG AIC_SMR[32]; // Source Mode Register AT91_REG AIC_SVR[32]; // Source Vector Register AT91_REG AIC_IVR; // IRQ Vector Register AT91_REG AIC_FVR; // FIQ Vector Register AT91_REG AIC_ISR; // Interrupt Status Register AT91_REG AIC_IPR; // Interrupt Pending Register AT91_REG AIC_IMR; // Interrupt Mask Register AT91_REG AIC_CISR; // Core Interrupt Status Register AT91_REG Reserved0[2]; // AT91_REG AIC_IECR; // Interrupt Enable Command Register AT91_REG AIC_IDCR; // Interrupt Disable Command Register AT91_REG AIC_ICCR; // Interrupt Clear Command Register AT91_REG AIC_ISCR; // Interrupt Set Command Register AT91_REG AIC_EOICR; // End of Interrupt Command Register AT91_REG AIC_SPU; // Spurious Vector Register AT91_REG AIC_DCR; // Debug Control Register (Protect) AT91_REG Reserved1[1]; // AT91_REG AIC_FFER; // Fast Forcing Enable Register AT91_REG AIC_FFDR; // Fast Forcing Disable Register AT91_REG AIC_FFSR; // Fast Forcing Status Register } AT91S_AIC, *AT91PS_AIC; #else #define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register #define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register #define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register #define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register #define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register #define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register #define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register #define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register #define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register #define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register #define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register #define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register #define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register #define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register #define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect) #define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register #define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register #define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register #endif // -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- #define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level #define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level #define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level #define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type #define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive #define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered #define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive #define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered // -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- #define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status #define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status // -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- #define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode #define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask // ***************************************************************************** // SOFTWARE API DEFINITION FOR Parallel Input Output Controler // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_PIO { AT91_REG PIO_PER; // PIO Enable Register AT91_REG PIO_PDR; // PIO Disable Register AT91_REG PIO_PSR; // PIO Status Register AT91_REG Reserved0[1]; // AT91_REG PIO_OER; // Output Enable Register AT91_REG PIO_ODR; // Output Disable Registerr AT91_REG PIO_OSR; // Output Status Register AT91_REG Reserved1[1]; // AT91_REG PIO_IFER; // Input Filter Enable Register AT91_REG PIO_IFDR; // Input Filter Disable Register AT91_REG PIO_IFSR; // Input Filter Status Register AT91_REG Reserved2[1]; // AT91_REG PIO_SODR; // Set Output Data Register AT91_REG PIO_CODR; // Clear Output Data Register AT91_REG PIO_ODSR; // Output Data Status Register AT91_REG PIO_PDSR; // Pin Data Status Register AT91_REG PIO_IER; // Interrupt Enable Register AT91_REG PIO_IDR; // Interrupt Disable Register AT91_REG PIO_IMR; // Interrupt Mask Register AT91_REG PIO_ISR; // Interrupt Status Register AT91_REG PIO_MDER; // Multi-driver Enable Register AT91_REG PIO_MDDR; // Multi-driver Disable Register AT91_REG PIO_MDSR; // Multi-driver Status Register AT91_REG Reserved3[1]; // AT91_REG PIO_PPUDR; // Pull-up Disable Register AT91_REG PIO_PPUER; // Pull-up Enable Register AT91_REG PIO_PPUSR; // Pull-up Status Register AT91_REG Reserved4[1]; // AT91_REG PIO_ASR; // Select A Register AT91_REG PIO_BSR; // Select B Register AT91_REG PIO_ABSR; // AB Select Status Register AT91_REG Reserved5[9]; // AT91_REG PIO_OWER; // Output Write Enable Register AT91_REG PIO_OWDR; // Output Write Disable Register AT91_REG PIO_OWSR; // Output Write Status Register } AT91S_PIO, *AT91PS_PIO; #else #define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register #define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register #define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register #define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register #define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr #define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register #define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register #define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register #define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register #define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register #define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register #define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register #define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register #define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register #define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register #define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register #define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register #define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register #define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register #define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register #define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register #define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register #define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register #define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register #define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register #define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register #define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register #define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register #define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register #endif // ***************************************************************************** // SOFTWARE API DEFINITION FOR Clock Generator Controler // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_CKGR { AT91_REG CKGR_MOR; // Main Oscillator Register AT91_REG CKGR_MCFR; // Main Clock Frequency Register AT91_REG CKGR_PLLAR; // PLL A Register AT91_REG CKGR_PLLBR; // PLL B Register } AT91S_CKGR, *AT91PS_CKGR; #else #define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register #define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register #define CKGR_PLLAR (AT91_CAST(AT91_REG *) 0x00000008) // (CKGR_PLLAR) PLL A Register #define CKGR_PLLBR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLBR) PLL B Register #endif // -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- #define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable #define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass #define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time // -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- #define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency #define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready // -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- #define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider A Selected #define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider A output is 0 #define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider A is bypassed #define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter #define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range #define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet #define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet #define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet #define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet #define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier #define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR) // -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- #define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider B Selected #define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider B output is 0 #define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider B is bypassed #define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter #define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range #define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet #define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet #define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet #define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet #define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier #define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks #define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output #define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 #define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 // ***************************************************************************** // SOFTWARE API DEFINITION FOR Power Management Controler // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_PMC { AT91_REG PMC_SCER; // System Clock Enable Register AT91_REG PMC_SCDR; // System Clock Disable Register AT91_REG PMC_SCSR; // System Clock Status Register AT91_REG Reserved0[1]; // AT91_REG PMC_PCER; // Peripheral Clock Enable Register AT91_REG PMC_PCDR; // Peripheral Clock Disable Register AT91_REG PMC_PCSR; // Peripheral Clock Status Register AT91_REG Reserved1[1]; // AT91_REG PMC_MOR; // Main Oscillator Register AT91_REG PMC_MCFR; // Main Clock Frequency Register AT91_REG PMC_PLLAR; // PLL A Register AT91_REG PMC_PLLBR; // PLL B Register AT91_REG PMC_MCKR; // Master Clock Register AT91_REG Reserved2[3]; // AT91_REG PMC_PCKR[8]; // Programmable Clock Register AT91_REG PMC_IER; // Interrupt Enable Register AT91_REG PMC_IDR; // Interrupt Disable Register AT91_REG PMC_SR; // Status Register AT91_REG PMC_IMR; // Interrupt Mask Register } AT91S_PMC, *AT91PS_PMC; #else #define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register #define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register #define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register #define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register #define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register #define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register #define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register #define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register #define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register #define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register #define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register #define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register #endif // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- #define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock #define AT91C_PMC_OTG (0x1 << 5) // (PMC) USB OTG Clock #define AT91C_PMC_UHP (0x1 << 6) // (PMC) USB Host Port Clock #define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock #define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- // -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- // -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- // -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- // -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register -------- // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- #define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection #define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected #define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected #define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected #define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected #define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler #define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock #define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 #define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 #define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 #define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 #define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 #define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 #define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division #define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same #define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock #define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is four times faster than the master clock // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- #define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask #define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask #define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask #define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask #define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Reset Controller Interface // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_RSTC { AT91_REG RSTC_RCR; // Reset Control Register AT91_REG RSTC_RSR; // Reset Status Register AT91_REG RSTC_RMR; // Reset Mode Register } AT91S_RSTC, *AT91PS_RSTC; #else #define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register #define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register #define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register #endif // -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- #define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset #define AT91C_RSTC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset #define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset #define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset #define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password // -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- #define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status #define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type #define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising. #define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. #define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. #define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. #define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. #define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level #define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. // -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- #define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable #define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable #define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable // ***************************************************************************** // SOFTWARE API DEFINITION FOR Shut Down Controller Interface // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_SHDWC { AT91_REG SHDWC_SHCR; // Shut Down Control Register AT91_REG SHDWC_SHMR; // Shut Down Mode Register AT91_REG SHDWC_SHSR; // Shut Down Status Register } AT91S_SHDWC, *AT91PS_SHDWC; #else #define SHDWC_SHCR (AT91_CAST(AT91_REG *) 0x00000000) // (SHDWC_SHCR) Shut Down Control Register #define SHDWC_SHMR (AT91_CAST(AT91_REG *) 0x00000004) // (SHDWC_SHMR) Shut Down Mode Register #define SHDWC_SHSR (AT91_CAST(AT91_REG *) 0x00000008) // (SHDWC_SHSR) Shut Down Status Register #endif // -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register -------- #define AT91C_SHDWC_SHDW (0x1 << 0) // (SHDWC) Processor Reset #define AT91C_SHDWC_KEY (0xFF << 24) // (SHDWC) Shut down KEY Password // -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register -------- #define AT91C_SHDWC_WKMODE0 (0x3 << 0) // (SHDWC) Wake Up 0 Mode Selection #define AT91C_SHDWC_WKMODE0_NONE (0x0) // (SHDWC) None. No detection is performed on the wake up input. #define AT91C_SHDWC_WKMODE0_HIGH (0x1) // (SHDWC) High Level. #define AT91C_SHDWC_WKMODE0_LOW (0x2) // (SHDWC) Low Level. #define AT91C_SHDWC_WKMODE0_ANYLEVEL (0x3) // (SHDWC) Any level change. #define AT91C_SHDWC_CPTWK0 (0xF << 4) // (SHDWC) Counter On Wake Up 0 #define AT91C_SHDWC_RTTWKEN (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable // -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register -------- #define AT91C_SHDWC_WAKEUP0 (0x1 << 0) // (SHDWC) Wake Up 0 Status #define AT91C_SHDWC_RTTWK (0x1 << 16) // (SHDWC) Real Time Timer wake Up // ***************************************************************************** // SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_RTTC { AT91_REG RTTC_RTMR; // Real-time Mode Register AT91_REG RTTC_RTAR; // Real-time Alarm Register AT91_REG RTTC_RTVR; // Real-time Value Register AT91_REG RTTC_RTSR; // Real-time Status Register } AT91S_RTTC, *AT91PS_RTTC; #else #define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register #define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register #define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register #define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register #endif // -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- #define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value #define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable #define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable #define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart // -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- #define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value // -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- #define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value // -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- #define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status #define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment // ***************************************************************************** // SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_PITC { AT91_REG PITC_PIMR; // Period Interval Mode Register AT91_REG PITC_PISR; // Period Interval Status Register AT91_REG PITC_PIVR; // Period Interval Value Register AT91_REG PITC_PIIR; // Period Interval Image Register } AT91S_PITC, *AT91PS_PITC; #else #define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register #define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register #define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register #define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register #endif // -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- #define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value #define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled #define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable // -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- #define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status // -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- #define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value #define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter // -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_WDTC { AT91_REG WDTC_WDCR; // Watchdog Control Register AT91_REG WDTC_WDMR; // Watchdog Mode Register AT91_REG WDTC_WDSR; // Watchdog Status Register } AT91S_WDTC, *AT91PS_WDTC; #else #define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register #define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register #define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register #endif // -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- #define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart #define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password // -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- #define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart #define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable #define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable #define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart #define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable #define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value #define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt #define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt // -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- #define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow #define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error // ***************************************************************************** // SOFTWARE API DEFINITION FOR Timer Counter Channel Interface // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_TC { AT91_REG TC_CCR; // Channel Control Register AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) AT91_REG Reserved0[2]; // AT91_REG TC_CV; // Counter Value AT91_REG TC_RA; // Register A AT91_REG TC_RB; // Register B AT91_REG TC_RC; // Register C AT91_REG TC_SR; // Status Register AT91_REG TC_IER; // Interrupt Enable Register AT91_REG TC_IDR; // Interrupt Disable Register AT91_REG TC_IMR; // Interrupt Mask Register } AT91S_TC, *AT91PS_TC; #else #define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register #define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) #define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value #define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A #define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B #define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C #define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register #define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register #define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register #define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register #endif // -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- #define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command #define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command #define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command // -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- #define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK #define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK #define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 #define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 #define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 #define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert #define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection #define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal #define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock #define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock #define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock #define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare #define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading #define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare #define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading #define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection #define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None #define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge #define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge #define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge #define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection #define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None #define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge #define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge #define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge #define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection #define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input #define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output #define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output #define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output #define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection #define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable #define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection #define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare #define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare #define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare #define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare #define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable #define AT91C_TC_WAVE (0x1 << 15) // (TC) #define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA #define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none #define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set #define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear #define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle #define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection #define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None #define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA #define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA #define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA #define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA #define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none #define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set #define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear #define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle #define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection #define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None #define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA #define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA #define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA #define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA #define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none #define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set #define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear #define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle #define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA #define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none #define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set #define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear #define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle #define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB #define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none #define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set #define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear #define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle #define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB #define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none #define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set #define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear #define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle #define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB #define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none #define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set #define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear #define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle #define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB #define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none #define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set #define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear #define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle // -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- #define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow #define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun #define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare #define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare #define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare #define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading #define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading #define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger #define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling #define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror #define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror // -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- // -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- // -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Timer Counter Interface // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_TCB { AT91S_TC TCB_TC0; // TC Channel 0 AT91_REG Reserved0[4]; // AT91S_TC TCB_TC1; // TC Channel 1 AT91_REG Reserved1[4]; // AT91S_TC TCB_TC2; // TC Channel 2 AT91_REG Reserved2[4]; // AT91_REG TCB_BCR; // TC Block Control Register AT91_REG TCB_BMR; // TC Block Mode Register } AT91S_TCB, *AT91PS_TCB; #else #define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register #define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register #endif // -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- #define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command // -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- #define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection #define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 #define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 #define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 #define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 #define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection #define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 #define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 #define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 #define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 #define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection #define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 #define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 #define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 #define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 // ***************************************************************************** // SOFTWARE API DEFINITION FOR Multimedia Card Interface // ***************************************************************************** #ifndef __ASSEMBLY__ typedef struct _AT91S_MCI { AT91_REG MCI_CR; // MCI Control Register AT91_REG MCI_MR; // MCI Mode Register AT91_REG MCI_DTOR; // MCI Data Timeout Register AT91_REG MCI_SDCR; // MCI SD Card Register AT91_REG MCI_ARGR; // MCI Argument Register AT91_REG MCI_CMDR; // MCI Command Register AT91_REG MCI_BLKR; // MCI Block Register AT91_REG Reserved0[1]; // AT91_REG MCI_RSPR[4]; // MCI Response Register AT91_REG MCI_RDR; // MCI Receive Data Register AT91_REG MCI_TDR; // MCI Transmit Data Register AT91_REG Reserved1[2]; // AT91_REG MCI_SR; // MCI Status Register AT91_REG MCI_IER; // MCI Interrupt Enable Register AT91_REG MCI_IDR; // MCI Interrupt Disable Register AT91_REG MCI_IMR; // MCI Interrupt Mask Register AT91_REG Reserved2[43]; // AT91_REG MCI_VR; // MCI Version Register AT91_REG MCI_RPR; // Receive Pointer Register AT91_REG MCI_RCR; // Receive Counter Register AT91_REG MCI_TPR; // Transmit Pointer Register AT91_REG MCI_TCR; // Transmit Counter Register AT91_REG MCI_RNPR; // Receive Next Pointer Register AT91_REG MCI_RNCR; // Receive Next Counter Register AT91_REG MCI_TNPR; // Transmit Next Pointer Register AT91_REG MCI_TNCR; // Transmit Next Counter Register AT91_REG MCI_PTCR; // PDC Transfer Control Register AT91_REG MCI_PTSR; // PDC Transfer Status Register } AT91S_MCI, *AT91PS_MCI; #else #define MCI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (MCI_CR) MCI Control Register #define MCI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (MCI_MR) MCI Mode Register #define MCI_DTOR (AT91_CAST(AT91_REG *) 0x00000008) // (MCI_DTOR) MCI Data Timeout Register #define MCI_SDCR (AT91_CAST(AT91_REG *) 0x0000000C) // (MCI_SDCR) MCI SD Card Register #define MCI_ARGR (AT91_CAST(AT91_REG *) 0x00000010) // (MCI_ARGR) MCI Argument Register #define MCI_CMDR (AT91_CAST(AT91_REG *) 0x00000014) // (MCI_CMDR) MCI Command Register #define MCI_BLKR (AT91_CAST(AT91_REG *) 0x00000018) // (MCI_BLKR) MCI Block Register #define MCI_RSPR (AT91_CAST(AT91_REG *) 0x00000020) // (MCI_RSPR) MCI Response Register #define MCI_RDR (AT91_CAST(AT91_REG *) 0x00000030) // (MCI_RDR) MCI Receive Data Register #define MCI_TDR (AT91_CAST(AT91_REG *) 0x00000034) // (MCI_TDR) MCI Transmit Data Register #define MCI_SR (AT91_CAST(AT91_REG *) 0x00000040) // (MCI_SR) MCI Status Register #define MCI_IER (AT91_CAST(AT91_REG *) 0x00000044) // (MCI_IER) MCI Interrupt Enable Register #define MCI_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (MCI_IDR) MCI Interrupt Disable Regist