// ---------------------------------------------------------------------------- // ATMEL Microcontroller Software Support - ROUSSET - // ---------------------------------------------------------------------------- // DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR // IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE // DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, // OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, // EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // ---------------------------------------------------------------------------- // File Name : AT91SAM9261.h // Object : AT91SAM9261 definitions // Generated : AT91 SW Application Group 09/12/2005 (15:39:27) // // CVS Reference : /AT91SAM9261.pl/1.12/Mon Sep 12 13:26:48 2005// // CVS Reference : /SYS_SAM9261.pl/1.5/Thu Nov 18 13:22:33 2004// // CVS Reference : /HMATRIX1_SAM9261.pl/1.2/Mon Nov 8 16:38:17 2004// // CVS Reference : /PMC_SAM9261.pl/1.4/Fri Sep 9 15:24:01 2005// // CVS Reference : /HSMC3_SAM9261.pl/1.1/Tue Nov 16 09:16:07 2004// // CVS Reference : /SHDWC_SAM9261.pl/1.1/Tue Mar 8 14:46:52 2005// // CVS Reference : /UDP_SAM9261.pl/1.1/Tue May 10 12:39:24 2005// // CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 9 10:52:25 2004// // CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005// // CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005// // CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005// // CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005// // CVS Reference : /RSTC_6098A.pl/1.3/Thu Nov 4 13:57:00 2004// // CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004// // CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004// // CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004// // CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005// // CVS Reference : /MCI_6101A.pl/1.1/Tue Jul 13 06:33:59 2004// // CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 06:38:23 2004// // CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005// // CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:25:46 2005// // CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005// // CVS Reference : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005// // CVS Reference : /LCDC_6063A.pl/1.2/Wed Nov 24 15:55:51 2004// // ---------------------------------------------------------------------------- #ifndef AT91SAM9261_H #define AT91SAM9261_H typedef volatile unsigned int AT91_REG;// Hardware register definition // ***************************************************************************** // SOFTWARE API DEFINITION FOR System Peripherals // ***************************************************************************** typedef struct _AT91S_SYS { AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register AT91_REG Reserved0[118]; // AT91_REG SMC_SETUP0; // Setup Register for CS 0 AT91_REG SMC_PULSE0; // Pulse Register for CS 0 AT91_REG SMC_CYCLE0; // Cycle Register for CS 0 AT91_REG SMC_CTRL0; // Control Register for CS 0 AT91_REG SMC_SETUP1; // Setup Register for CS 1 AT91_REG SMC_PULSE1; // Pulse Register for CS 1 AT91_REG SMC_CYCLE1; // Cycle Register for CS 1 AT91_REG SMC_CTRL1; // Control Register for CS 1 AT91_REG SMC_SETUP2; // Setup Register for CS 2 AT91_REG SMC_PULSE2; // Pulse Register for CS 2 AT91_REG SMC_CYCLE2; // Cycle Register for CS 2 AT91_REG SMC_CTRL2; // Control Register for CS 2 AT91_REG SMC_SETUP3; // Setup Register for CS 3 AT91_REG SMC_PULSE3; // Pulse Register for CS 3 AT91_REG SMC_CYCLE3; // Cycle Register for CS 3 AT91_REG SMC_CTRL3; // Control Register for CS 3 AT91_REG SMC_SETUP4; // Setup Register for CS 4 AT91_REG SMC_PULSE4; // Pulse Register for CS 4 AT91_REG SMC_CYCLE4; // Cycle Register for CS 4 AT91_REG SMC_CTRL4; // Control Register for CS 4 AT91_REG SMC_SETUP5; // Setup Register for CS 5 AT91_REG SMC_PULSE5; // Pulse Register for CS 5 AT91_REG SMC_CYCLE5; // Cycle Register for CS 5 AT91_REG SMC_CTRL5; // Control Register for CS 5 AT91_REG SMC_SETUP6; // Setup Register for CS 6 AT91_REG SMC_PULSE6; // Pulse Register for CS 6 AT91_REG SMC_CYCLE6; // Cycle Register for CS 6 AT91_REG SMC_CTRL6; // Control Register for CS 6 AT91_REG SMC_SETUP7; // Setup Register for CS 7 AT91_REG SMC_PULSE7; // Pulse Register for CS 7 AT91_REG SMC_CYCLE7; // Cycle Register for CS 7 AT91_REG SMC_CTRL7; // Control Register for CS 7 AT91_REG Reserved1[96]; // AT91_REG MATRIX_MCFG; // Master Configuration Register AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 AT91_REG Reserved2[3]; // AT91_REG MATRIX_TCMR; // Slave 0 Special Function Register AT91_REG Reserved3[2]; // AT91_REG MATRIX_EBICSA; // Slave 3 Special Function Register AT91_REG MATRIX_USBPCR; // Slave 4 Special Function Register AT91_REG Reserved4[3]; // AT91_REG MATRIX_VERSION; // Version Register AT91_REG Reserved5[110]; // AT91_REG AIC_SMR[32]; // Source Mode Register AT91_REG AIC_SVR[32]; // Source Vector Register AT91_REG AIC_IVR; // IRQ Vector Register AT91_REG AIC_FVR; // FIQ Vector Register AT91_REG AIC_ISR; // Interrupt Status Register AT91_REG AIC_IPR; // Interrupt Pending Register AT91_REG AIC_IMR; // Interrupt Mask Register AT91_REG AIC_CISR; // Core Interrupt Status Register AT91_REG Reserved6[2]; // AT91_REG AIC_IECR; // Interrupt Enable Command Register AT91_REG AIC_IDCR; // Interrupt Disable Command Register AT91_REG AIC_ICCR; // Interrupt Clear Command Register AT91_REG AIC_ISCR; // Interrupt Set Command Register AT91_REG AIC_EOICR; // End of Interrupt Command Register AT91_REG AIC_SPU; // Spurious Vector Register AT91_REG AIC_DCR; // Debug Control Register (Protect) AT91_REG Reserved7[1]; // AT91_REG AIC_FFER; // Fast Forcing Enable Register AT91_REG AIC_FFDR; // Fast Forcing Disable Register AT91_REG AIC_FFSR; // Fast Forcing Status Register AT91_REG Reserved8[45]; // AT91_REG DBGU_CR; // Control Register AT91_REG DBGU_MR; // Mode Register AT91_REG DBGU_IER; // Interrupt Enable Register AT91_REG DBGU_IDR; // Interrupt Disable Register AT91_REG DBGU_IMR; // Interrupt Mask Register AT91_REG DBGU_CSR; // Channel Status Register AT91_REG DBGU_RHR; // Receiver Holding Register AT91_REG DBGU_THR; // Transmitter Holding Register AT91_REG DBGU_BRGR; // Baud Rate Generator Register AT91_REG Reserved9[7]; // AT91_REG DBGU_CIDR; // Chip ID Register AT91_REG DBGU_EXID; // Chip ID Extension Register AT91_REG DBGU_FNTR; // Force NTRST Register AT91_REG Reserved10[45]; // AT91_REG DBGU_RPR; // Receive Pointer Register AT91_REG DBGU_RCR; // Receive Counter Register AT91_REG DBGU_TPR; // Transmit Pointer Register AT91_REG DBGU_TCR; // Transmit Counter Register AT91_REG DBGU_RNPR; // Receive Next Pointer Register AT91_REG DBGU_RNCR; // Receive Next Counter Register AT91_REG DBGU_TNPR; // Transmit Next Pointer Register AT91_REG DBGU_TNCR; // Transmit Next Counter Register AT91_REG DBGU_PTCR; // PDC Transfer Control Register AT91_REG DBGU_PTSR; // PDC Transfer Status Register AT91_REG Reserved11[54]; // AT91_REG PIOA_PER; // PIO Enable Register AT91_REG PIOA_PDR; // PIO Disable Register AT91_REG PIOA_PSR; // PIO Status Register AT91_REG Reserved12[1]; // AT91_REG PIOA_OER; // Output Enable Register AT91_REG PIOA_ODR; // Output Disable Registerr AT91_REG PIOA_OSR; // Output Status Register AT91_REG Reserved13[1]; // AT91_REG PIOA_IFER; // Input Filter Enable Register AT91_REG PIOA_IFDR; // Input Filter Disable Register AT91_REG PIOA_IFSR; // Input Filter Status Register AT91_REG Reserved14[1]; // AT91_REG PIOA_SODR; // Set Output Data Register AT91_REG PIOA_CODR; // Clear Output Data Register AT91_REG PIOA_ODSR; // Output Data Status Register AT91_REG PIOA_PDSR; // Pin Data Status Register AT91_REG PIOA_IER; // Interrupt Enable Register AT91_REG PIOA_IDR; // Interrupt Disable Register AT91_REG PIOA_IMR; // Interrupt Mask Register AT91_REG PIOA_ISR; // Interrupt Status Register AT91_REG PIOA_MDER; // Multi-driver Enable Register AT91_REG PIOA_MDDR; // Multi-driver Disable Register AT91_REG PIOA_MDSR; // Multi-driver Status Register AT91_REG Reserved15[1]; // AT91_REG PIOA_PPUDR; // Pull-up Disable Register AT91_REG PIOA_PPUER; // Pull-up Enable Register AT91_REG PIOA_PPUSR; // Pull-up Status Register AT91_REG Reserved16[1]; // AT91_REG PIOA_ASR; // Select A Register AT91_REG PIOA_BSR; // Select B Register AT91_REG PIOA_ABSR; // AB Select Status Register AT91_REG Reserved17[9]; // AT91_REG PIOA_OWER; // Output Write Enable Register AT91_REG PIOA_OWDR; // Output Write Disable Register AT91_REG PIOA_OWSR; // Output Write Status Register AT91_REG Reserved18[85]; // AT91_REG PIOB_PER; // PIO Enable Register AT91_REG PIOB_PDR; // PIO Disable Register AT91_REG PIOB_PSR; // PIO Status Register AT91_REG Reserved19[1]; // AT91_REG PIOB_OER; // Output Enable Register AT91_REG PIOB_ODR; // Output Disable Registerr AT91_REG PIOB_OSR; // Output Status Register AT91_REG Reserved20[1]; // AT91_REG PIOB_IFER; // Input Filter Enable Register AT91_REG PIOB_IFDR; // Input Filter Disable Register AT91_REG PIOB_IFSR; // Input Filter Status Register AT91_REG Reserved21[1]; // AT91_REG PIOB_SODR; // Set Output Data Register AT91_REG PIOB_CODR; // Clear Output Data Register AT91_REG PIOB_ODSR; // Output Data Status Register AT91_REG PIOB_PDSR; // Pin Data Status Register AT91_REG PIOB_IER; // Interrupt Enable Register AT91_REG PIOB_IDR; // Interrupt Disable Register AT91_REG PIOB_IMR; // Interrupt Mask Register AT91_REG PIOB_ISR; // Interrupt Status Register AT91_REG PIOB_MDER; // Multi-driver Enable Register AT91_REG PIOB_MDDR; // Multi-driver Disable Register AT91_REG PIOB_MDSR; // Multi-driver Status Register AT91_REG Reserved22[1]; // AT91_REG PIOB_PPUDR; // Pull-up Disable Register AT91_REG PIOB_PPUER; // Pull-up Enable Register AT91_REG PIOB_PPUSR; // Pull-up Status Register AT91_REG Reserved23[1]; // AT91_REG PIOB_ASR; // Select A Register AT91_REG PIOB_BSR; // Select B Register AT91_REG PIOB_ABSR; // AB Select Status Register AT91_REG Reserved24[9]; // AT91_REG PIOB_OWER; // Output Write Enable Register AT91_REG PIOB_OWDR; // Output Write Disable Register AT91_REG PIOB_OWSR; // Output Write Status Register AT91_REG Reserved25[85]; // AT91_REG PIOC_PER; // PIO Enable Register AT91_REG PIOC_PDR; // PIO Disable Register AT91_REG PIOC_PSR; // PIO Status Register AT91_REG Reserved26[1]; // AT91_REG PIOC_OER; // Output Enable Register AT91_REG PIOC_ODR; // Output Disable Registerr AT91_REG PIOC_OSR; // Output Status Register AT91_REG Reserved27[1]; // AT91_REG PIOC_IFER; // Input Filter Enable Register AT91_REG PIOC_IFDR; // Input Filter Disable Register AT91_REG PIOC_IFSR; // Input Filter Status Register AT91_REG Reserved28[1]; // AT91_REG PIOC_SODR; // Set Output Data Register AT91_REG PIOC_CODR; // Clear Output Data Register AT91_REG PIOC_ODSR; // Output Data Status Register AT91_REG PIOC_PDSR; // Pin Data Status Register AT91_REG PIOC_IER; // Interrupt Enable Register AT91_REG PIOC_IDR; // Interrupt Disable Register AT91_REG PIOC_IMR; // Interrupt Mask Register AT91_REG PIOC_ISR; // Interrupt Status Register AT91_REG PIOC_MDER; // Multi-driver Enable Register AT91_REG PIOC_MDDR; // Multi-driver Disable Register AT91_REG PIOC_MDSR; // Multi-driver Status Register AT91_REG Reserved29[1]; // AT91_REG PIOC_PPUDR; // Pull-up Disable Register AT91_REG PIOC_PPUER; // Pull-up Enable Register AT91_REG PIOC_PPUSR; // Pull-up Status Register AT91_REG Reserved30[1]; // AT91_REG PIOC_ASR; // Select A Register AT91_REG PIOC_BSR; // Select B Register AT91_REG PIOC_ABSR; // AB Select Status Register AT91_REG Reserved31[9]; // AT91_REG PIOC_OWER; // Output Write Enable Register AT91_REG PIOC_OWDR; // Output Write Disable Register AT91_REG PIOC_OWSR; // Output Write Status Register AT91_REG Reserved32[213]; // AT91_REG PMC_SCER; // System Clock Enable Register AT91_REG PMC_SCDR; // System Clock Disable Register AT91_REG PMC_SCSR; // System Clock Status Register AT91_REG Reserved33[1]; // AT91_REG PMC_PCER; // Peripheral Clock Enable Register AT91_REG PMC_PCDR; // Peripheral Clock Disable Register AT91_REG PMC_PCSR; // Peripheral Clock Status Register AT91_REG Reserved34[1]; // AT91_REG PMC_MOR; // Main Oscillator Register AT91_REG PMC_MCFR; // Main Clock Frequency Register AT91_REG PMC_PLLAR; // PLL A Register AT91_REG PMC_PLLBR; // PLL B Register AT91_REG PMC_MCKR; // Master Clock Register AT91_REG Reserved35[3]; // AT91_REG PMC_PCKR[8]; // Programmable Clock Register AT91_REG PMC_IER; // Interrupt Enable Register AT91_REG PMC_IDR; // Interrupt Disable Register AT91_REG PMC_SR; // Status Register AT91_REG PMC_IMR; // Interrupt Mask Register AT91_REG Reserved36[36]; // AT91_REG RSTC_RCR; // Reset Control Register AT91_REG RSTC_RSR; // Reset Status Register AT91_REG RSTC_RMR; // Reset Mode Register AT91_REG Reserved37[1]; // AT91_REG SHDWC_SHCR; // Shut Down Control Register AT91_REG SHDWC_SHMR; // Shut Down Mode Register AT91_REG SHDWC_SHSR; // Shut Down Status Register AT91_REG Reserved38[1]; // AT91_REG RTTC_RTMR; // Real-time Mode Register AT91_REG RTTC_RTAR; // Real-time Alarm Register AT91_REG RTTC_RTVR; // Real-time Value Register AT91_REG RTTC_RTSR; // Real-time Status Register AT91_REG PITC_PIMR; // Period Interval Mode Register AT91_REG PITC_PISR; // Period Interval Status Register AT91_REG PITC_PIVR; // Period Interval Value Register AT91_REG PITC_PIIR; // Period Interval Image Register AT91_REG WDTC_WDCR; // Watchdog Control Register AT91_REG WDTC_WDMR; // Watchdog Mode Register AT91_REG WDTC_WDSR; // Watchdog Status Register AT91_REG Reserved39[1]; // AT91_REG SYS_GPBR0; // General Purpose Register 0 AT91_REG SYS_GPBR1; // General Purpose Register 1 AT91_REG SYS_GPBR2; // General Purpose Register 2 AT91_REG SYS_GPBR3; // General Purpose Register 3 } AT91S_SYS, *AT91PS_SYS; // -------- GPBR : (SYS Offset: 0x1350) GPBR General Purpose Register -------- // -------- GPBR : (SYS Offset: 0x1354) GPBR General Purpose Register -------- // -------- GPBR : (SYS Offset: 0x1358) GPBR General Purpose Register -------- // -------- GPBR : (SYS Offset: 0x135c) GPBR General Purpose Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR SDRAM Controller Interface // ***************************************************************************** typedef struct _AT91S_SDRAMC { AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register } AT91S_SDRAMC, *AT91PS_SDRAMC; // -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register -------- #define AT91C_SDRAMC_MODE ((unsigned int) 0xF << 0) // (SDRAMC) Mode #define AT91C_SDRAMC_MODE_NORMAL_CMD ((unsigned int) 0x0) // (SDRAMC) Normal Mode #define AT91C_SDRAMC_MODE_NOP_CMD ((unsigned int) 0x1) // (SDRAMC) Issue a NOP Command at every access #define AT91C_SDRAMC_MODE_PRCGALL_CMD ((unsigned int) 0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access #define AT91C_SDRAMC_MODE_LMR_CMD ((unsigned int) 0x3) // (SDRAMC) Issue a Load Mode Register at every access #define AT91C_SDRAMC_MODE_RFSH_CMD ((unsigned int) 0x4) // (SDRAMC) Issue a Refresh #define AT91C_SDRAMC_MODE_EXT_LMR_CMD ((unsigned int) 0x5) // (SDRAMC) Issue an Extended Load Mode Register #define AT91C_SDRAMC_MODE_DEEP_CMD ((unsigned int) 0x6) // (SDRAMC) Enter Deep Power Mode // -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register -------- #define AT91C_SDRAMC_COUNT ((unsigned int) 0xFFF << 0) // (SDRAMC) Refresh Counter // -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register -------- #define AT91C_SDRAMC_NC ((unsigned int) 0x3 << 0) // (SDRAMC) Number of Column Bits #define AT91C_SDRAMC_NC_8 ((unsigned int) 0x0) // (SDRAMC) 8 Bits #define AT91C_SDRAMC_NC_9 ((unsigned int) 0x1) // (SDRAMC) 9 Bits #define AT91C_SDRAMC_NC_10 ((unsigned int) 0x2) // (SDRAMC) 10 Bits #define AT91C_SDRAMC_NC_11 ((unsigned int) 0x3) // (SDRAMC) 11 Bits #define AT91C_SDRAMC_NR ((unsigned int) 0x3 << 2) // (SDRAMC) Number of Row Bits #define AT91C_SDRAMC_NR_11 ((unsigned int) 0x0 << 2) // (SDRAMC) 11 Bits #define AT91C_SDRAMC_NR_12 ((unsigned int) 0x1 << 2) // (SDRAMC) 12 Bits #define AT91C_SDRAMC_NR_13 ((unsigned int) 0x2 << 2) // (SDRAMC) 13 Bits #define AT91C_SDRAMC_NB ((unsigned int) 0x1 << 4) // (SDRAMC) Number of Banks #define AT91C_SDRAMC_NB_2_BANKS ((unsigned int) 0x0 << 4) // (SDRAMC) 2 banks #define AT91C_SDRAMC_NB_4_BANKS ((unsigned int) 0x1 << 4) // (SDRAMC) 4 banks #define AT91C_SDRAMC_CAS ((unsigned int) 0x3 << 5) // (SDRAMC) CAS Latency #define AT91C_SDRAMC_CAS_2 ((unsigned int) 0x2 << 5) // (SDRAMC) 2 cycles #define AT91C_SDRAMC_CAS_3 ((unsigned int) 0x3 << 5) // (SDRAMC) 3 cycles #define AT91C_SDRAMC_DBW ((unsigned int) 0x1 << 7) // (SDRAMC) Data Bus Width #define AT91C_SDRAMC_DBW_32_BITS ((unsigned int) 0x0 << 7) // (SDRAMC) 32 Bits datas bus #define AT91C_SDRAMC_DBW_16_BITS ((unsigned int) 0x1 << 7) // (SDRAMC) 16 Bits datas bus #define AT91C_SDRAMC_TWR ((unsigned int) 0xF << 8) // (SDRAMC) Number of Write Recovery Time Cycles #define AT91C_SDRAMC_TWR_0 ((unsigned int) 0x0 << 8) // (SDRAMC) Value : 0 #define AT91C_SDRAMC_TWR_1 ((unsigned int) 0x1 << 8) // (SDRAMC) Value : 1 #define AT91C_SDRAMC_TWR_2 ((unsigned int) 0x2 << 8) // (SDRAMC) Value : 2 #define AT91C_SDRAMC_TWR_3 ((unsigned int) 0x3 << 8) // (SDRAMC) Value : 3 #define AT91C_SDRAMC_TWR_4 ((unsigned int) 0x4 << 8) // (SDRAMC) Value : 4 #define AT91C_SDRAMC_TWR_5 ((unsigned int) 0x5 << 8) // (SDRAMC) Value : 5 #define AT91C_SDRAMC_TWR_6 ((unsigned int) 0x6 << 8) // (SDRAMC) Value : 6 #define AT91C_SDRAMC_TWR_7 ((unsigned int) 0x7 << 8) // (SDRAMC) Value : 7 #define AT91C_SDRAMC_TWR_8 ((unsigned int) 0x8 << 8) // (SDRAMC) Value : 8 #define AT91C_SDRAMC_TWR_9 ((unsigned int) 0x9 << 8) // (SDRAMC) Value : 9 #define AT91C_SDRAMC_TWR_10 ((unsigned int) 0xA << 8) // (SDRAMC) Value : 10 #define AT91C_SDRAMC_TWR_11 ((unsigned int) 0xB << 8) // (SDRAMC) Value : 11 #define AT91C_SDRAMC_TWR_12 ((unsigned int) 0xC << 8) // (SDRAMC) Value : 12 #define AT91C_SDRAMC_TWR_13 ((unsigned int) 0xD << 8) // (SDRAMC) Value : 13 #define AT91C_SDRAMC_TWR_14 ((unsigned int) 0xE << 8) // (SDRAMC) Value : 14 #define AT91C_SDRAMC_TWR_15 ((unsigned int) 0xF << 8) // (SDRAMC) Value : 15 #define AT91C_SDRAMC_TRC ((unsigned int) 0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles #define AT91C_SDRAMC_TRC_0 ((unsigned int) 0x0 << 12) // (SDRAMC) Value : 0 #define AT91C_SDRAMC_TRC_1 ((unsigned int) 0x1 << 12) // (SDRAMC) Value : 1 #define AT91C_SDRAMC_TRC_2 ((unsigned int) 0x2 << 12) // (SDRAMC) Value : 2 #define AT91C_SDRAMC_TRC_3 ((unsigned int) 0x3 << 12) // (SDRAMC) Value : 3 #define AT91C_SDRAMC_TRC_4 ((unsigned int) 0x4 << 12) // (SDRAMC) Value : 4 #define AT91C_SDRAMC_TRC_5 ((unsigned int) 0x5 << 12) // (SDRAMC) Value : 5 #define AT91C_SDRAMC_TRC_6 ((unsigned int) 0x6 << 12) // (SDRAMC) Value : 6 #define AT91C_SDRAMC_TRC_7 ((unsigned int) 0x7 << 12) // (SDRAMC) Value : 7 #define AT91C_SDRAMC_TRC_8 ((unsigned int) 0x8 << 12) // (SDRAMC) Value : 8 #define AT91C_SDRAMC_TRC_9 ((unsigned int) 0x9 << 12) // (SDRAMC) Value : 9 #define AT91C_SDRAMC_TRC_10 ((unsigned int) 0xA << 12) // (SDRAMC) Value : 10 #define AT91C_SDRAMC_TRC_11 ((unsigned int) 0xB << 12) // (SDRAMC) Value : 11 #define AT91C_SDRAMC_TRC_12 ((unsigned int) 0xC << 12) // (SDRAMC) Value : 12 #define AT91C_SDRAMC_TRC_13 ((unsigned int) 0xD << 12) // (SDRAMC) Value : 13 #define AT91C_SDRAMC_TRC_14 ((unsigned int) 0xE << 12) // (SDRAMC) Value : 14 #define AT91C_SDRAMC_TRC_15 ((unsigned int) 0xF << 12) // (SDRAMC) Value : 15 #define AT91C_SDRAMC_TRP ((unsigned int) 0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles #define AT91C_SDRAMC_TRP_0 ((unsigned int) 0x0 << 16) // (SDRAMC) Value : 0 #define AT91C_SDRAMC_TRP_1 ((unsigned int) 0x1 << 16) // (SDRAMC) Value : 1 #define AT91C_SDRAMC_TRP_2 ((unsigned int) 0x2 << 16) // (SDRAMC) Value : 2 #define AT91C_SDRAMC_TRP_3 ((unsigned int) 0x3 << 16) // (SDRAMC) Value : 3 #define AT91C_SDRAMC_TRP_4 ((unsigned int) 0x4 << 16) // (SDRAMC) Value : 4 #define AT91C_SDRAMC_TRP_5 ((unsigned int) 0x5 << 16) // (SDRAMC) Value : 5 #define AT91C_SDRAMC_TRP_6 ((unsigned int) 0x6 << 16) // (SDRAMC) Value : 6 #define AT91C_SDRAMC_TRP_7 ((unsigned int) 0x7 << 16) // (SDRAMC) Value : 7 #define AT91C_SDRAMC_TRP_8 ((unsigned int) 0x8 << 16) // (SDRAMC) Value : 8 #define AT91C_SDRAMC_TRP_9 ((unsigned int) 0x9 << 16) // (SDRAMC) Value : 9 #define AT91C_SDRAMC_TRP_10 ((unsigned int) 0xA << 16) // (SDRAMC) Value : 10 #define AT91C_SDRAMC_TRP_11 ((unsigned int) 0xB << 16) // (SDRAMC) Value : 11 #define AT91C_SDRAMC_TRP_12 ((unsigned int) 0xC << 16) // (SDRAMC) Value : 12 #define AT91C_SDRAMC_TRP_13 ((unsigned int) 0xD << 16) // (SDRAMC) Value : 13 #define AT91C_SDRAMC_TRP_14 ((unsigned int) 0xE << 16) // (SDRAMC) Value : 14 #define AT91C_SDRAMC_TRP_15 ((unsigned int) 0xF << 16) // (SDRAMC) Value : 15 #define AT91C_SDRAMC_TRCD ((unsigned int) 0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles #define AT91C_SDRAMC_TRCD_0 ((unsigned int) 0x0 << 20) // (SDRAMC) Value : 0 #define AT91C_SDRAMC_TRCD_1 ((unsigned int) 0x1 << 20) // (SDRAMC) Value : 1 #define AT91C_SDRAMC_TRCD_2 ((unsigned int) 0x2 << 20) // (SDRAMC) Value : 2 #define AT91C_SDRAMC_TRCD_3 ((unsigned int) 0x3 << 20) // (SDRAMC) Value : 3 #define AT91C_SDRAMC_TRCD_4 ((unsigned int) 0x4 << 20) // (SDRAMC) Value : 4 #define AT91C_SDRAMC_TRCD_5 ((unsigned int) 0x5 << 20) // (SDRAMC) Value : 5 #define AT91C_SDRAMC_TRCD_6 ((unsigned int) 0x6 << 20) // (SDRAMC) Value : 6 #define AT91C_SDRAMC_TRCD_7 ((unsigned int) 0x7 << 20) // (SDRAMC) Value : 7 #define AT91C_SDRAMC_TRCD_8 ((unsigned int) 0x8 << 20) // (SDRAMC) Value : 8 #define AT91C_SDRAMC_TRCD_9 ((unsigned int) 0x9 << 20) // (SDRAMC) Value : 9 #define AT91C_SDRAMC_TRCD_10 ((unsigned int) 0xA << 20) // (SDRAMC) Value : 10 #define AT91C_SDRAMC_TRCD_11 ((unsigned int) 0xB << 20) // (SDRAMC) Value : 11 #define AT91C_SDRAMC_TRCD_12 ((unsigned int) 0xC << 20) // (SDRAMC) Value : 12 #define AT91C_SDRAMC_TRCD_13 ((unsigned int) 0xD << 20) // (SDRAMC) Value : 13 #define AT91C_SDRAMC_TRCD_14 ((unsigned int) 0xE << 20) // (SDRAMC) Value : 14 #define AT91C_SDRAMC_TRCD_15 ((unsigned int) 0xF << 20) // (SDRAMC) Value : 15 #define AT91C_SDRAMC_TRAS ((unsigned int) 0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles #define AT91C_SDRAMC_TRAS_0 ((unsigned int) 0x0 << 24) // (SDRAMC) Value : 0 #define AT91C_SDRAMC_TRAS_1 ((unsigned int) 0x1 << 24) // (SDRAMC) Value : 1 #define AT91C_SDRAMC_TRAS_2 ((unsigned int) 0x2 << 24) // (SDRAMC) Value : 2 #define AT91C_SDRAMC_TRAS_3 ((unsigned int) 0x3 << 24) // (SDRAMC) Value : 3 #define AT91C_SDRAMC_TRAS_4 ((unsigned int) 0x4 << 24) // (SDRAMC) Value : 4 #define AT91C_SDRAMC_TRAS_5 ((unsigned int) 0x5 << 24) // (SDRAMC) Value : 5 #define AT91C_SDRAMC_TRAS_6 ((unsigned int) 0x6 << 24) // (SDRAMC) Value : 6 #define AT91C_SDRAMC_TRAS_7 ((unsigned int) 0x7 << 24) // (SDRAMC) Value : 7 #define AT91C_SDRAMC_TRAS_8 ((unsigned int) 0x8 << 24) // (SDRAMC) Value : 8 #define AT91C_SDRAMC_TRAS_9 ((unsigned int) 0x9 << 24) // (SDRAMC) Value : 9 #define AT91C_SDRAMC_TRAS_10 ((unsigned int) 0xA << 24) // (SDRAMC) Value : 10 #define AT91C_SDRAMC_TRAS_11 ((unsigned int) 0xB << 24) // (SDRAMC) Value : 11 #define AT91C_SDRAMC_TRAS_12 ((unsigned int) 0xC << 24) // (SDRAMC) Value : 12 #define AT91C_SDRAMC_TRAS_13 ((unsigned int) 0xD << 24) // (SDRAMC) Value : 13 #define AT91C_SDRAMC_TRAS_14 ((unsigned int) 0xE << 24) // (SDRAMC) Value : 14 #define AT91C_SDRAMC_TRAS_15 ((unsigned int) 0xF << 24) // (SDRAMC) Value : 15 #define AT91C_SDRAMC_TXSR ((unsigned int) 0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles #define AT91C_SDRAMC_TXSR_0 ((unsigned int) 0x0 << 28) // (SDRAMC) Value : 0 #define AT91C_SDRAMC_TXSR_1 ((unsigned int) 0x1 << 28) // (SDRAMC) Value : 1 #define AT91C_SDRAMC_TXSR_2 ((unsigned int) 0x2 << 28) // (SDRAMC) Value : 2 #define AT91C_SDRAMC_TXSR_3 ((unsigned int) 0x3 << 28) // (SDRAMC) Value : 3 #define AT91C_SDRAMC_TXSR_4 ((unsigned int) 0x4 << 28) // (SDRAMC) Value : 4 #define AT91C_SDRAMC_TXSR_5 ((unsigned int) 0x5 << 28) // (SDRAMC) Value : 5 #define AT91C_SDRAMC_TXSR_6 ((unsigned int) 0x6 << 28) // (SDRAMC) Value : 6 #define AT91C_SDRAMC_TXSR_7 ((unsigned int) 0x7 << 28) // (SDRAMC) Value : 7 #define AT91C_SDRAMC_TXSR_8 ((unsigned int) 0x8 << 28) // (SDRAMC) Value : 8 #define AT91C_SDRAMC_TXSR_9 ((unsigned int) 0x9 << 28) // (SDRAMC) Value : 9 #define AT91C_SDRAMC_TXSR_10 ((unsigned int) 0xA << 28) // (SDRAMC) Value : 10 #define AT91C_SDRAMC_TXSR_11 ((unsigned int) 0xB << 28) // (SDRAMC) Value : 11 #define AT91C_SDRAMC_TXSR_12 ((unsigned int) 0xC << 28) // (SDRAMC) Value : 12 #define AT91C_SDRAMC_TXSR_13 ((unsigned int) 0xD << 28) // (SDRAMC) Value : 13 #define AT91C_SDRAMC_TXSR_14 ((unsigned int) 0xE << 28) // (SDRAMC) Value : 14 #define AT91C_SDRAMC_TXSR_15 ((unsigned int) 0xF << 28) // (SDRAMC) Value : 15 // -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register -------- #define AT91C_SDRAMC_DA ((unsigned int) 0x1 << 0) // (SDRAMC) Decode Cycle Enable Bit #define AT91C_SDRAMC_DA_DISABLE ((unsigned int) 0x0) // (SDRAMC) Disable Decode Cycle #define AT91C_SDRAMC_DA_ENABLE ((unsigned int) 0x1) // (SDRAMC) Enable Decode Cycle // -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register -------- #define AT91C_SDRAMC_LPCB ((unsigned int) 0x3 << 0) // (SDRAMC) Low-power Configurations #define AT91C_SDRAMC_LPCB_DISABLE ((unsigned int) 0x0) // (SDRAMC) Disable Low Power Features #define AT91C_SDRAMC_LPCB_SELF_REFRESH ((unsigned int) 0x1) // (SDRAMC) Enable SELF_REFRESH #define AT91C_SDRAMC_LPCB_POWER_DOWN ((unsigned int) 0x2) // (SDRAMC) Enable POWER_DOWN #define AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN ((unsigned int) 0x3) // (SDRAMC) Enable DEEP_POWER_DOWN #define AT91C_SDRAMC_PASR ((unsigned int) 0x7 << 4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM) #define AT91C_SDRAMC_TCSR ((unsigned int) 0x3 << 8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM) #define AT91C_SDRAMC_DS ((unsigned int) 0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM) #define AT91C_SDRAMC_TIMEOUT ((unsigned int) 0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled #define AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES ((unsigned int) 0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately #define AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES ((unsigned int) 0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer #define AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES ((unsigned int) 0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer // -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register -------- #define AT91C_SDRAMC_RES ((unsigned int) 0x1 << 0) // (SDRAMC) Refresh Error Status // -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register -------- // -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register -------- // -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register -------- // -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register -------- #define AT91C_SDRAMC_MD ((unsigned int) 0x3 << 0) // (SDRAMC) Memory Device Type #define AT91C_SDRAMC_MD_SDRAM ((unsigned int) 0x0) // (SDRAMC) SDRAM Mode #define AT91C_SDRAMC_MD_LOW_POWER_SDRAM ((unsigned int) 0x1) // (SDRAMC) SDRAM Low Power Mode // ***************************************************************************** // SOFTWARE API DEFINITION FOR Static Memory Controller Interface // ***************************************************************************** typedef struct _AT91S_SMC { AT91_REG SMC_SETUP0; // Setup Register for CS 0 AT91_REG SMC_PULSE0; // Pulse Register for CS 0 AT91_REG SMC_CYCLE0; // Cycle Register for CS 0 AT91_REG SMC_CTRL0; // Control Register for CS 0 AT91_REG SMC_SETUP1; // Setup Register for CS 1 AT91_REG SMC_PULSE1; // Pulse Register for CS 1 AT91_REG SMC_CYCLE1; // Cycle Register for CS 1 AT91_REG SMC_CTRL1; // Control Register for CS 1 AT91_REG SMC_SETUP2; // Setup Register for CS 2 AT91_REG SMC_PULSE2; // Pulse Register for CS 2 AT91_REG SMC_CYCLE2; // Cycle Register for CS 2 AT91_REG SMC_CTRL2; // Control Register for CS 2 AT91_REG SMC_SETUP3; // Setup Register for CS 3 AT91_REG SMC_PULSE3; // Pulse Register for CS 3 AT91_REG SMC_CYCLE3; // Cycle Register for CS 3 AT91_REG SMC_CTRL3; // Control Register for CS 3 AT91_REG SMC_SETUP4; // Setup Register for CS 4 AT91_REG SMC_PULSE4; // Pulse Register for CS 4 AT91_REG SMC_CYCLE4; // Cycle Register for CS 4 AT91_REG SMC_CTRL4; // Control Register for CS 4 AT91_REG SMC_SETUP5; // Setup Register for CS 5 AT91_REG SMC_PULSE5; // Pulse Register for CS 5 AT91_REG SMC_CYCLE5; // Cycle Register for CS 5 AT91_REG SMC_CTRL5; // Control Register for CS 5 AT91_REG SMC_SETUP6; // Setup Register for CS 6 AT91_REG SMC_PULSE6; // Pulse Register for CS 6 AT91_REG SMC_CYCLE6; // Cycle Register for CS 6 AT91_REG SMC_CTRL6; // Control Register for CS 6 AT91_REG SMC_SETUP7; // Setup Register for CS 7 AT91_REG SMC_PULSE7; // Pulse Register for CS 7 AT91_REG SMC_CYCLE7; // Cycle Register for CS 7 AT91_REG SMC_CTRL7; // Control Register for CS 7 } AT91S_SMC, *AT91PS_SMC; // -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x -------- #define AT91C_SMC_NWESETUP ((unsigned int) 0x3F << 0) // (SMC) NWE Setup Length #define AT91C_SMC_NCSSETUPWR ((unsigned int) 0x3F << 8) // (SMC) NCS Setup Length in WRite Access #define AT91C_SMC_NRDSETUP ((unsigned int) 0x3F << 16) // (SMC) NRD Setup Length #define AT91C_SMC_NCSSETUPRD ((unsigned int) 0x3F << 24) // (SMC) NCS Setup Length in ReaD Access // -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x -------- #define AT91C_SMC_NWEPULSE ((unsigned int) 0x7F << 0) // (SMC) NWE Pulse Length #define AT91C_SMC_NCSPULSEWR ((unsigned int) 0x7F << 8) // (SMC) NCS Pulse Length in WRite Access #define AT91C_SMC_NRDPULSE ((unsigned int) 0x7F << 16) // (SMC) NRD Pulse Length #define AT91C_SMC_NCSPULSERD ((unsigned int) 0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access // -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x -------- #define AT91C_SMC_NWECYCLE ((unsigned int) 0x1FF << 0) // (SMC) Total Write Cycle Length #define AT91C_SMC_NRDCYCLE ((unsigned int) 0x1FF << 16) // (SMC) Total Read Cycle Length // -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x -------- #define AT91C_SMC_READMODE ((unsigned int) 0x1 << 0) // (SMC) Read Mode #define AT91C_SMC_WRITEMODE ((unsigned int) 0x1 << 1) // (SMC) Write Mode #define AT91C_SMC_NWAITM ((unsigned int) 0x3 << 5) // (SMC) NWAIT Mode #define AT91C_SMC_NWAITM_NWAIT_DISABLE ((unsigned int) 0x0 << 5) // (SMC) External NWAIT disabled. #define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN ((unsigned int) 0x2 << 5) // (SMC) External NWAIT enabled in frozen mode. #define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY ((unsigned int) 0x3 << 5) // (SMC) External NWAIT enabled in ready mode. #define AT91C_SMC_BAT ((unsigned int) 0x1 << 8) // (SMC) Byte Access Type #define AT91C_SMC_BAT_BYTE_SELECT ((unsigned int) 0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. #define AT91C_SMC_BAT_BYTE_WRITE ((unsigned int) 0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. #define AT91C_SMC_DBW ((unsigned int) 0x3 << 12) // (SMC) Data Bus Width #define AT91C_SMC_DBW_WIDTH_EIGTH_BITS ((unsigned int) 0x0 << 12) // (SMC) 8 bits. #define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS ((unsigned int) 0x1 << 12) // (SMC) 16 bits. #define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS ((unsigned int) 0x2 << 12) // (SMC) 32 bits. #define AT91C_SMC_TDF ((unsigned int) 0xF << 16) // (SMC) Data Float Time. #define AT91C_SMC_TDFEN ((unsigned int) 0x1 << 20) // (SMC) TDF Enabled. #define AT91C_SMC_PMEN ((unsigned int) 0x1 << 24) // (SMC) Page Mode Enabled. #define AT91C_SMC_PS ((unsigned int) 0x3 << 28) // (SMC) Page Size #define AT91C_SMC_PS_SIZE_FOUR_BYTES ((unsigned int) 0x0 << 28) // (SMC) 4 bytes. #define AT91C_SMC_PS_SIZE_EIGHT_BYTES ((unsigned int) 0x1 << 28) // (SMC) 8 bytes. #define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES ((unsigned int) 0x2 << 28) // (SMC) 16 bytes. #define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES ((unsigned int) 0x3 << 28) // (SMC) 32 bytes. // -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x -------- // -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x -------- // -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x -------- // -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x -------- // -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR AHB Matrix Interface // ***************************************************************************** typedef struct _AT91S_MATRIX { AT91_REG MATRIX_MCFG; // Master Configuration Register AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0 AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1 AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2 AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3 AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4 AT91_REG Reserved0[3]; // AT91_REG MATRIX_TCMR; // Slave 0 Special Function Register AT91_REG Reserved1[2]; // AT91_REG MATRIX_EBICSA; // Slave 3 Special Function Register AT91_REG MATRIX_USBPCR; // Slave 4 Special Function Register AT91_REG Reserved2[3]; // AT91_REG MATRIX_VERSION; // Version Register } AT91S_MATRIX, *AT91PS_MATRIX; // -------- MATRIX_MCFG : (MATRIX Offset: 0x0) Master Configuration Register -------- #define AT91C_MATRIX_RCA926I ((unsigned int) 0x1 << 0) // (MATRIX) Remap Command for ARM926EJ-S Instruction Master #define AT91C_MATRIX_RCA926D ((unsigned int) 0x1 << 1) // (MATRIX) Remap Command for ARM926EJ-S Data Master // -------- MATRIX_SCFG0 : (MATRIX Offset: 0x4) Slave Configuration Register 0 -------- #define AT91C_MATRIX_SLOT_CYCLE ((unsigned int) 0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst #define AT91C_MATRIX_DEFMSTR_TYPE ((unsigned int) 0x3 << 16) // (MATRIX) Default Master Type #define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR ((unsigned int) 0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. #define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR ((unsigned int) 0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. #define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR ((unsigned int) 0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. #define AT91C_MATRIX_FIXED_DEFMSTR0 ((unsigned int) 0x7 << 18) // (MATRIX) Fixed Index of Default Master #define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I ((unsigned int) 0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D ((unsigned int) 0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3 ((unsigned int) 0x2 << 18) // (MATRIX) HPDC3 Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC ((unsigned int) 0x3 << 18) // (MATRIX) LCDC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR0_UHP ((unsigned int) 0x4 << 18) // (MATRIX) UHP Master is Default Master // -------- MATRIX_SCFG1 : (MATRIX Offset: 0x8) Slave Configuration Register 1 -------- #define AT91C_MATRIX_FIXED_DEFMSTR1 ((unsigned int) 0x7 << 18) // (MATRIX) Fixed Index of Default Master #define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I ((unsigned int) 0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D ((unsigned int) 0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3 ((unsigned int) 0x2 << 18) // (MATRIX) HPDC3 Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC ((unsigned int) 0x3 << 18) // (MATRIX) LCDC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR1_UHP ((unsigned int) 0x4 << 18) // (MATRIX) UHP Master is Default Master // -------- MATRIX_SCFG2 : (MATRIX Offset: 0xc) Slave Configuration Register 2 -------- #define AT91C_MATRIX_FIXED_DEFMSTR2 ((unsigned int) 0x1 << 18) // (MATRIX) Fixed Index of Default Master #define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I ((unsigned int) 0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D ((unsigned int) 0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master // -------- MATRIX_SCFG3 : (MATRIX Offset: 0x10) Slave Configuration Register 3 -------- #define AT91C_MATRIX_FIXED_DEFMSTR3 ((unsigned int) 0x7 << 18) // (MATRIX) Fixed Index of Default Master #define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I ((unsigned int) 0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D ((unsigned int) 0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3 ((unsigned int) 0x2 << 18) // (MATRIX) HPDC3 Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC ((unsigned int) 0x3 << 18) // (MATRIX) LCDC Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR3_UHP ((unsigned int) 0x4 << 18) // (MATRIX) UHP Master is Default Master // -------- MATRIX_SCFG4 : (MATRIX Offset: 0x14) Slave Configuration Register 4 -------- #define AT91C_MATRIX_FIXED_DEFMSTR4 ((unsigned int) 0x3 << 18) // (MATRIX) Fixed Index of Default Master #define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I ((unsigned int) 0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D ((unsigned int) 0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master #define AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3 ((unsigned int) 0x2 << 18) // (MATRIX) HPDC3 Master is Default Master // -------- MATRIX_TCMR : (MATRIX Offset: 0x24) TCM (Slave 0) Special Function Register -------- #define AT91C_MATRIX_ITCM_SIZE ((unsigned int) 0xF << 0) // (MATRIX) Size of ITCM enabled memory block #define AT91C_MATRIX_ITCM_SIZE_0KB ((unsigned int) 0x0) // (MATRIX) 0 KB (No ITCM Memory) #define AT91C_MATRIX_ITCM_SIZE_16KB ((unsigned int) 0x5) // (MATRIX) 16 KB #define AT91C_MATRIX_ITCM_SIZE_32KB ((unsigned int) 0x6) // (MATRIX) 32 KB #define AT91C_MATRIX_ITCM_SIZE_64KB ((unsigned int) 0x7) // (MATRIX) 64 KB #define AT91C_MATRIX_DTCM_SIZE ((unsigned int) 0xF << 4) // (MATRIX) Size of DTCM enabled memory block #define AT91C_MATRIX_DTCM_SIZE_0KB ((unsigned int) 0x0 << 4) // (MATRIX) 0 KB (No DTCM Memory) #define AT91C_MATRIX_DTCM_SIZE_16KB ((unsigned int) 0x5 << 4) // (MATRIX) 16 KB #define AT91C_MATRIX_DTCM_SIZE_32KB ((unsigned int) 0x6 << 4) // (MATRIX) 32 KB #define AT91C_MATRIX_DTCM_SIZE_64KB ((unsigned int) 0x7 << 4) // (MATRIX) 64 KB // -------- MATRIX_EBICSA : (MATRIX Offset: 0x30) EBI (Slave 3) Special Function Register -------- #define AT91C_MATRIX_CS1A ((unsigned int) 0x1 << 1) // (MATRIX) Chip Select 1 Assignment #define AT91C_MATRIX_CS1A_SMC ((unsigned int) 0x0 << 1) // (MATRIX) Chip Select 1 is assigned to the Static Memory Controller. #define AT91C_MATRIX_CS1A_SDRAMC ((unsigned int) 0x1 << 1) // (MATRIX) Chip Select 1 is assigned to the SDRAM Controller. #define AT91C_MATRIX_CS3A ((unsigned int) 0x1 << 3) // (MATRIX) Chip Select 3 Assignment #define AT91C_MATRIX_CS3A_SMC ((unsigned int) 0x0 << 3) // (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC. #define AT91C_MATRIX_CS3A_SM ((unsigned int) 0x1 << 3) // (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. #define AT91C_MATRIX_CS4A ((unsigned int) 0x1 << 4) // (MATRIX) Chip Select 4 Assignment #define AT91C_MATRIX_CS4A_SMC ((unsigned int) 0x0 << 4) // (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC. #define AT91C_MATRIX_CS4A_CF ((unsigned int) 0x1 << 4) // (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated. #define AT91C_MATRIX_CS5A ((unsigned int) 0x1 << 5) // (MATRIX) Chip Select 5 Assignment #define AT91C_MATRIX_CS5A_SMC ((unsigned int) 0x0 << 5) // (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC #define AT91C_MATRIX_CS5A_CF ((unsigned int) 0x1 << 5) // (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated. #define AT91C_MATRIX_DBPUC ((unsigned int) 0x1 << 8) // (MATRIX) Data Bus Pull-up Configuration // -------- MATRIX_USBPCR : (MATRIX Offset: 0x34) USB Pad Control Register -------- #define AT91C_MATRIX_USBPCR_PUON ((unsigned int) 0x1 << 30) // (MATRIX) PullUp On #define AT91C_MATRIX_USBPCR_PUIDLE ((unsigned int) 0x1 << 31) // (MATRIX) PullUp Idle // ***************************************************************************** // SOFTWARE API DEFINITION FOR Advanced Interrupt Controller // ***************************************************************************** typedef struct _AT91S_AIC { AT91_REG AIC_SMR[32]; // Source Mode Register AT91_REG AIC_SVR[32]; // Source Vector Register AT91_REG AIC_IVR; // IRQ Vector Register AT91_REG AIC_FVR; // FIQ Vector Register AT91_REG AIC_ISR; // Interrupt Status Register AT91_REG AIC_IPR; // Interrupt Pending Register AT91_REG AIC_IMR; // Interrupt Mask Register AT91_REG AIC_CISR; // Core Interrupt Status Register AT91_REG Reserved0[2]; // AT91_REG AIC_IECR; // Interrupt Enable Command Register AT91_REG AIC_IDCR; // Interrupt Disable Command Register AT91_REG AIC_ICCR; // Interrupt Clear Command Register AT91_REG AIC_ISCR; // Interrupt Set Command Register AT91_REG AIC_EOICR; // End of Interrupt Command Register AT91_REG AIC_SPU; // Spurious Vector Register AT91_REG AIC_DCR; // Debug Control Register (Protect) AT91_REG Reserved1[1]; // AT91_REG AIC_FFER; // Fast Forcing Enable Register AT91_REG AIC_FFDR; // Fast Forcing Disable Register AT91_REG AIC_FFSR; // Fast Forcing Status Register } AT91S_AIC, *AT91PS_AIC; // -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- #define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level #define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level #define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level #define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type #define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive #define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered #define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive #define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered // -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- #define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status #define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status // -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- #define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode #define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask // ***************************************************************************** // SOFTWARE API DEFINITION FOR Peripheral DMA Controller // ***************************************************************************** typedef struct _AT91S_PDC { AT91_REG PDC_RPR; // Receive Pointer Register AT91_REG PDC_RCR; // Receive Counter Register AT91_REG PDC_TPR; // Transmit Pointer Register AT91_REG PDC_TCR; // Transmit Counter Register AT91_REG PDC_RNPR; // Receive Next Pointer Register AT91_REG PDC_RNCR; // Receive Next Counter Register AT91_REG PDC_TNPR; // Transmit Next Pointer Register AT91_REG PDC_TNCR; // Transmit Next Counter Register AT91_REG PDC_PTCR; // PDC Transfer Control Register AT91_REG PDC_PTSR; // PDC Transfer Status Register } AT91S_PDC, *AT91PS_PDC; // -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- #define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable #define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable #define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable #define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable // -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Debug Unit // ***************************************************************************** typedef struct _AT91S_DBGU { AT91_REG DBGU_CR; // Control Register AT91_REG DBGU_MR; // Mode Register AT91_REG DBGU_IER; // Interrupt Enable Register AT91_REG DBGU_IDR; // Interrupt Disable Register AT91_REG DBGU_IMR; // Interrupt Mask Register AT91_REG DBGU_CSR; // Channel Status Register AT91_REG DBGU_RHR; // Receiver Holding Register AT91_REG DBGU_THR; // Transmitter Holding Register AT91_REG DBGU_BRGR; // Baud Rate Generator Register AT91_REG Reserved0[7]; // AT91_REG DBGU_CIDR; // Chip ID Register AT91_REG DBGU_EXID; // Chip ID Extension Register AT91_REG DBGU_FNTR; // Force NTRST Register AT91_REG Reserved1[45]; // AT91_REG DBGU_RPR; // Receive Pointer Register AT91_REG DBGU_RCR; // Receive Counter Register AT91_REG DBGU_TPR; // Transmit Pointer Register AT91_REG DBGU_TCR; // Transmit Counter Register AT91_REG DBGU_RNPR; // Receive Next Pointer Register AT91_REG DBGU_RNCR; // Receive Next Counter Register AT91_REG DBGU_TNPR; // Transmit Next Pointer Register AT91_REG DBGU_TNCR; // Transmit Next Counter Register AT91_REG DBGU_PTCR; // PDC Transfer Control Register AT91_REG DBGU_PTSR; // PDC Transfer Status Register } AT91S_DBGU, *AT91PS_DBGU; // -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- #define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver #define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter #define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable #define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable #define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable #define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable #define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits // -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- #define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type #define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity #define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity #define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) #define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) #define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity #define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode #define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode #define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. #define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. #define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. #define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. // -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- #define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt #define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt #define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt #define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt #define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt #define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt #define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt #define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt #define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt #define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt #define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt #define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt // -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- #define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG // ***************************************************************************** // SOFTWARE API DEFINITION FOR Parallel Input Output Controler // ***************************************************************************** typedef struct _AT91S_PIO { AT91_REG PIO_PER; // PIO Enable Register AT91_REG PIO_PDR; // PIO Disable Register AT91_REG PIO_PSR; // PIO Status Register AT91_REG Reserved0[1]; // AT91_REG PIO_OER; // Output Enable Register AT91_REG PIO_ODR; // Output Disable Registerr AT91_REG PIO_OSR; // Output Status Register AT91_REG Reserved1[1]; // AT91_REG PIO_IFER; // Input Filter Enable Register AT91_REG PIO_IFDR; // Input Filter Disable Register AT91_REG PIO_IFSR; // Input Filter Status Register AT91_REG Reserved2[1]; // AT91_REG PIO_SODR; // Set Output Data Register AT91_REG PIO_CODR; // Clear Output Data Register AT91_REG PIO_ODSR; // Output Data Status Register AT91_REG PIO_PDSR; // Pin Data Status Register AT91_REG PIO_IER; // Interrupt Enable Register AT91_REG PIO_IDR; // Interrupt Disable Register AT91_REG PIO_IMR; // Interrupt Mask Register AT91_REG PIO_ISR; // Interrupt Status Register AT91_REG PIO_MDER; // Multi-driver Enable Register AT91_REG PIO_MDDR; // Multi-driver Disable Register AT91_REG PIO_MDSR; // Multi-driver Status Register AT91_REG Reserved3[1]; // AT91_REG PIO_PPUDR; // Pull-up Disable Register AT91_REG PIO_PPUER; // Pull-up Enable Register AT91_REG PIO_PPUSR; // Pull-up Status Register AT91_REG Reserved4[1]; // AT91_REG PIO_ASR; // Select A Register AT91_REG PIO_BSR; // Select B Register AT91_REG PIO_ABSR; // AB Select Status Register AT91_REG Reserved5[9]; // AT91_REG PIO_OWER; // Output Write Enable Register AT91_REG PIO_OWDR; // Output Write Disable Register AT91_REG PIO_OWSR; // Output Write Status Register } AT91S_PIO, *AT91PS_PIO; // ***************************************************************************** // SOFTWARE API DEFINITION FOR Clock Generator Controler // ***************************************************************************** typedef struct _AT91S_CKGR { AT91_REG CKGR_MOR; // Main Oscillator Register AT91_REG CKGR_MCFR; // Main Clock Frequency Register AT91_REG CKGR_PLLAR; // PLL A Register AT91_REG CKGR_PLLBR; // PLL B Register } AT91S_CKGR, *AT91PS_CKGR; // -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- #define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable #define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass #define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time // -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- #define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency #define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready // -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- #define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) // (CKGR) Divider A Selected #define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) // (CKGR) Divider A output is 0 #define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) // (CKGR) Divider A is bypassed #define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL A Counter #define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) // (CKGR) PLL A Output Frequency Range #define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLA datasheet #define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLA datasheet #define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLA datasheet #define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLA datasheet #define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) // (CKGR) PLL A Multiplier #define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) // (CKGR) // -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- #define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) // (CKGR) Divider B Selected #define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) // (CKGR) Divider B output is 0 #define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) // (CKGR) Divider B is bypassed #define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL B Counter #define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) // (CKGR) PLL B Output Frequency Range #define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLB datasheet #define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLB datasheet #define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLB datasheet #define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLB datasheet #define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) // (CKGR) PLL B Multiplier #define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks #define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output #define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 #define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 // ***************************************************************************** // SOFTWARE API DEFINITION FOR Power Management Controler // ***************************************************************************** typedef struct _AT91S_PMC { AT91_REG PMC_SCER; // System Clock Enable Register AT91_REG PMC_SCDR; // System Clock Disable Register AT91_REG PMC_SCSR; // System Clock Status Register AT91_REG Reserved0[1]; // AT91_REG PMC_PCER; // Peripheral Clock Enable Register AT91_REG PMC_PCDR; // Peripheral Clock Disable Register AT91_REG PMC_PCSR; // Peripheral Clock Status Register AT91_REG Reserved1[1]; // AT91_REG PMC_MOR; // Main Oscillator Register AT91_REG PMC_MCFR; // Main Clock Frequency Register AT91_REG PMC_PLLAR; // PLL A Register AT91_REG PMC_PLLBR; // PLL B Register AT91_REG PMC_MCKR; // Master Clock Register AT91_REG Reserved2[3]; // AT91_REG PMC_PCKR[8]; // Programmable Clock Register AT91_REG PMC_IER; // Interrupt Enable Register AT91_REG PMC_IDR; // Interrupt Disable Register AT91_REG PMC_SR; // Status Register AT91_REG PMC_IMR; // Interrupt Mask Register } AT91S_PMC, *AT91PS_PMC; // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- #define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock #define AT91C_PMC_UHP ((unsigned int) 0x1 << 6) // (PMC) USB Host Port Clock #define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock #define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output #define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output #define AT91C_PMC_HCK0 ((unsigned int) 0x1 << 16) // (PMC) AHB UHP Clock Output #define AT91C_PMC_HCK1 ((unsigned int) 0x1 << 17) // (PMC) AHB LCDC Clock Output // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- // -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- // -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- // -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- // -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register -------- // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- #define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection #define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected #define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected #define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) // (PMC) Clock from PLL A is selected #define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL B is selected #define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler #define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock #define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 #define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 #define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 #define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 #define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 #define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 #define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) // (PMC) Master Clock Division #define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) // (PMC) The master clock and the processor clock are the same #define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock #define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) // (PMC) The processor clock is four times faster than the master clock // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- #define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask #define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask #define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask #define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask #define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask #define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Reset Controller Interface // ***************************************************************************** typedef struct _AT91S_RSTC { AT91_REG RSTC_RCR; // Reset Control Register AT91_REG RSTC_RSR; // Reset Status Register AT91_REG RSTC_RMR; // Reset Mode Register } AT91S_RSTC, *AT91PS_RSTC; // -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- #define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset #define AT91C_RSTC_ICERST ((unsigned int) 0x1 << 1) // (RSTC) ICE Interface Reset #define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset #define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset #define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password // -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- #define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status #define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type #define AT91C_RSTC_RSTTYP_GENERAL ((unsigned int) 0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising. #define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. #define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. #define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. #define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. #define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level #define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. // -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- #define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable #define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable #define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Enable // ***************************************************************************** // SOFTWARE API DEFINITION FOR Shut Down Controller Interface // ***************************************************************************** typedef struct _AT91S_SHDWC { AT91_REG SHDWC_SHCR; // Shut Down Control Register AT91_REG SHDWC_SHMR; // Shut Down Mode Register AT91_REG SHDWC_SHSR; // Shut Down Status Register } AT91S_SHDWC, *AT91PS_SHDWC; // -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register -------- #define AT91C_SHDWC_SHDW ((unsigned int) 0x1 << 0) // (SHDWC) Processor Reset #define AT91C_SHDWC_KEY ((unsigned int) 0xFF << 24) // (SHDWC) Shut down KEY Password // -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register -------- #define AT91C_SHDWC_WKMODE0 ((unsigned int) 0x3 << 0) // (SHDWC) Wake Up 0 Mode Selection #define AT91C_SHDWC_WKMODE0_NONE ((unsigned int) 0x0) // (SHDWC) None. No detection is performed on the wake up input. #define AT91C_SHDWC_WKMODE0_HIGH ((unsigned int) 0x1) // (SHDWC) High Level. #define AT91C_SHDWC_WKMODE0_LOW ((unsigned int) 0x2) // (SHDWC) Low Level. #define AT91C_SHDWC_WKMODE0_ANYLEVEL ((unsigned int) 0x3) // (SHDWC) Any level change. #define AT91C_SHDWC_CPTWK0 ((unsigned int) 0xF << 4) // (SHDWC) Counter On Wake Up 0 #define AT91C_SHDWC_RTTWKEN ((unsigned int) 0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable // -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register -------- #define AT91C_SHDWC_WAKEUP0 ((unsigned int) 0x1 << 0) // (SHDWC) Wake Up 0 Status #define AT91C_SHDWC_RTTWK ((unsigned int) 0x1 << 16) // (SHDWC) Real Time Timer wake Up // ***************************************************************************** // SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface // ***************************************************************************** typedef struct _AT91S_RTTC { AT91_REG RTTC_RTMR; // Real-time Mode Register AT91_REG RTTC_RTAR; // Real-time Alarm Register AT91_REG RTTC_RTVR; // Real-time Value Register AT91_REG RTTC_RTSR; // Real-time Status Register } AT91S_RTTC, *AT91PS_RTTC; // -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- #define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value #define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable #define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable #define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart // -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- #define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value // -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- #define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value // -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- #define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status #define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment // ***************************************************************************** // SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface // ***************************************************************************** typedef struct _AT91S_PITC { AT91_REG PITC_PIMR; // Period Interval Mode Register AT91_REG PITC_PISR; // Period Interval Status Register AT91_REG PITC_PIVR; // Period Interval Value Register AT91_REG PITC_PIIR; // Period Interval Image Register } AT91S_PITC, *AT91PS_PITC; // -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- #define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value #define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled #define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable // -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- #define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status // -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- #define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value #define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter // -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface // ***************************************************************************** typedef struct _AT91S_WDTC { AT91_REG WDTC_WDCR; // Watchdog Control Register AT91_REG WDTC_WDMR; // Watchdog Mode Register AT91_REG WDTC_WDSR; // Watchdog Status Register } AT91S_WDTC, *AT91PS_WDTC; // -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- #define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart #define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password // -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- #define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart #define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable #define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable #define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart #define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable #define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value #define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt #define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt // -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- #define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow #define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error // ***************************************************************************** // SOFTWARE API DEFINITION FOR Timer Counter Channel Interface // ***************************************************************************** typedef struct _AT91S_TC { AT91_REG TC_CCR; // Channel Control Register AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) AT91_REG Reserved0[2]; // AT91_REG TC_CV; // Counter Value AT91_REG TC_RA; // Register A AT91_REG TC_RB; // Register B AT91_REG TC_RC; // Register C AT91_REG TC_SR; // Status Register AT91_REG TC_IER; // Interrupt Enable Register AT91_REG TC_IDR; // Interrupt Disable Register AT91_REG TC_IMR; // Interrupt Mask Register } AT91S_TC, *AT91PS_TC; // -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- #define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command #define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command #define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command // -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- #define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK #define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK #define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 #define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 #define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 #define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert #define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection #define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal #define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock #define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock #define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock #define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare #define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading #define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading #define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare #define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection #define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None #define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge #define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge #define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge #define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection #define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None #define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge #define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge #define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge #define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection #define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection #define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input #define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output #define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output #define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output #define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable #define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection #define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare #define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare #define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare #define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare #define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable #define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) #define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection #define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None #define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA #define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA #define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA #define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA #define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none #define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set #define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear #define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle #define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection #define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None #define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA #define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA #define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA #define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA #define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none #define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set #define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear #define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle #define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA #define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none #define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set #define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear #define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle #define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA #define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none #define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set #define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear #define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle #define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB #define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none #define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set #define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear #define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle #define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB #define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none #define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set #define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear #define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle #define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB #define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none #define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set #define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear #define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle #define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB #define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none #define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set #define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear #define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle // -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- #define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow #define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun #define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare #define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare #define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare #define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading #define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading #define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger #define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling #define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror #define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror // -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- // -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- // -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Timer Counter Interface // ***************************************************************************** typedef struct _AT91S_TCB { AT91S_TC TCB_TC0; // TC Channel 0 AT91_REG Reserved0[4]; // AT91S_TC TCB_TC1; // TC Channel 1 AT91_REG Reserved1[4]; // AT91S_TC TCB_TC2; // TC Channel 2 AT91_REG Reserved2[4]; // AT91_REG TCB_BCR; // TC Block Control Register AT91_REG TCB_BMR; // TC Block Mode Register } AT91S_TCB, *AT91PS_TCB; // -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- #define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command // -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- #define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection #define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 #define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 #define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 #define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 #define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection #define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 #define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 #define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 #define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 #define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection #define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 #define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 #define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 #define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 // ***************************************************************************** // SOFTWARE API DEFINITION FOR USB Device Interface // ***************************************************************************** typedef struct _AT91S_UDP { AT91_REG UDP_NUM; // Frame Number Register AT91_REG UDP_GLBSTATE; // Global State Register AT91_REG UDP_FADDR; // Function Address Register AT91_REG Reserved0[1]; // AT91_REG UDP_IER; // Interrupt Enable Register AT91_REG UDP_IDR; // Interrupt Disable Register AT91_REG UDP_IMR; // Interrupt Mask Register AT91_REG UDP_ISR; // Interrupt Status Register AT91_REG UDP_ICR; // Interrupt Clear Register AT91_REG Reserved1[1]; // AT91_REG UDP_RSTEP; // Reset Endpoint Register AT91_REG Reserved2[1]; // AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register AT91_REG Reserved3[2]; // AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register AT91_REG Reserved4[3]; // AT91_REG UDP_TXVC; // Transceiver Control Register } AT91S_UDP, *AT91PS_UDP; // -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- #define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats #define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error #define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK // -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- #define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable #define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured #define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume #define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host #define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable // -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- #define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value #define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable // -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- #define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt #define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt #define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt #define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt #define AT91C_UDP_EPINT4 ((unsigned int) 0x1 << 4) // (UDP) Endpoint 4 Interrupt #define AT91C_UDP_EPINT5 ((unsigned int) 0x1 << 5) // (UDP) Endpoint 5 Interrupt #define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt #define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt #define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt #define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt #define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt // -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- // -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- // -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- #define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt // -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- // -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- #define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 #define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 #define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 #define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 #define AT91C_UDP_EP4 ((unsigned int) 0x1 << 4) // (UDP) Reset Endpoint 4 #define AT91C_UDP_EP5 ((unsigned int) 0x1 << 5) // (UDP) Reset Endpoint 5 // -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- #define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR #define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 #define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) #define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) #define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready #define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). #define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). #define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction #define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type #define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control #define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT #define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT #define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT #define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN #define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN #define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN #define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle #define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable #define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO // -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- #define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) // ***************************************************************************** // SOFTWARE API DEFINITION FOR Multimedia Card Interface // ***************************************************************************** typedef struct _AT91S_MCI { AT91_REG MCI_CR; // MCI Control Register AT91_REG MCI_MR; // MCI Mode Register AT91_REG MCI_DTOR; // MCI Data Timeout Register AT91_REG MCI_SDCR; // MCI SD Card Register AT91_REG MCI_ARGR; // MCI Argument Register AT91_REG MCI_CMDR; // MCI Command Register AT91_REG Reserved0[2]; // AT91_REG MCI_RSPR[4]; // MCI Response Register AT91_REG MCI_RDR; // MCI Receive Data Register AT91_REG MCI_TDR; // MCI Transmit Data Register AT91_REG Reserved1[2]; // AT91_REG MCI_SR; // MCI Status Register AT91_REG MCI_IER; // MCI Interrupt Enable Register AT91_REG MCI_IDR; // MCI Interrupt Disable Register AT91_REG MCI_IMR; // MCI Interrupt Mask Register AT91_REG Reserved2[44]; // AT91_REG MCI_RPR; // Receive Pointer Register AT91_REG MCI_RCR; // Receive Counter Register AT91_REG MCI_TPR; // Transmit Pointer Register AT91_REG MCI_TCR; // Transmit Counter Register AT91_REG MCI_RNPR; // Receive Next Pointer Register AT91_REG MCI_RNCR; // Receive Next Counter Register AT91_REG MCI_TNPR; // Transmit Next Pointer Register AT91_REG MCI_TNCR; // Transmit Next Counter Register AT91_REG MCI_PTCR; // PDC Transfer Control Register AT91_REG MCI_PTSR; // PDC Transfer Status Register } AT91S_MCI, *AT91PS_MCI; // -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- #define AT91C_MCI_MCIEN ((unsigned int) 0x1 << 0) // (MCI) Multimedia Interface Enable #define AT91C_MCI_MCIDIS ((unsigned int) 0x1 << 1) // (MCI) Multimedia Interface Disable #define AT91C_MCI_PWSEN ((unsigned int) 0x1 << 2) // (MCI) Power Save Mode Enable #define AT91C_MCI_PWSDIS ((unsigned int) 0x1 << 3) // (MCI) Power Save Mode Disable #define AT91C_MCI_SWRST ((unsigned int) 0x1 << 7) // (MCI) MCI Software reset // -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- #define AT91C_MCI_CLKDIV ((unsigned int) 0xFF << 0) // (MCI) Clock Divider #define AT91C_MCI_PWSDIV ((unsigned int) 0x7 << 8) // (MCI) Power Saving Divider #define AT91C_MCI_PDCPADV ((unsigned int) 0x1 << 14) // (MCI) PDC Padding Value #define AT91C_MCI_PDCMODE ((unsigned int) 0x1 << 15) // (MCI) PDC Oriented Mode #define AT91C_MCI_BLKLEN ((unsigned int) 0xFFF << 18) // (MCI) Data Block Length // -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- #define AT91C_MCI_DTOCYC ((unsigned int) 0xF << 0) // (MCI) Data Timeout Cycle Number #define AT91C_MCI_DTOMUL ((unsigned int) 0x7 << 4) // (MCI) Data Timeout Multiplier #define AT91C_MCI_DTOMUL_1 ((unsigned int) 0x0 << 4) // (MCI) DTOCYC x 1 #define AT91C_MCI_DTOMUL_16 ((unsigned int) 0x1 << 4) // (MCI) DTOCYC x 16 #define AT91C_MCI_DTOMUL_128 ((unsigned int) 0x2 << 4) // (MCI) DTOCYC x 128 #define AT91C_MCI_DTOMUL_256 ((unsigned int) 0x3 << 4) // (MCI) DTOCYC x 256 #define AT91C_MCI_DTOMUL_1024 ((unsigned int) 0x4 << 4) // (MCI) DTOCYC x 1024 #define AT91C_MCI_DTOMUL_4096 ((unsigned int) 0x5 << 4) // (MCI) DTOCYC x 4096 #define AT91C_MCI_DTOMUL_65536 ((unsigned int) 0x6 << 4) // (MCI) DTOCYC x 65536 #define AT91C_MCI_DTOMUL_1048576 ((unsigned int) 0x7 << 4) // (MCI) DTOCYC x 1048576 // -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- #define AT91C_MCI_SCDSEL ((unsigned int) 0xF << 0) // (MCI) SD Card Selector #define AT91C_MCI_SCDBUS ((unsigned int) 0x1 << 7) // (MCI) SD Card Bus Width // -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- #define AT91C_MCI_CMDNB ((unsigned int) 0x3F << 0) // (MCI) Command Number #define AT91C_MCI_RSPTYP ((unsigned int) 0x3 << 6) // (MCI) Response Type #define AT91C_MCI_RSPTYP_NO ((unsigned int) 0x0 << 6) // (MCI) No response #define AT91C_MCI_RSPTYP_48 ((unsigned int) 0x1 << 6) // (MCI) 48-bit response #define AT91C_MCI_RSPTYP_136 ((unsigned int) 0x2 << 6) // (MCI) 136-bit response #define AT91C_MCI_SPCMD ((unsigned int) 0x7 << 8) // (MCI) Special CMD #define AT91C_MCI_SPCMD_NONE ((unsigned int) 0x0 << 8) // (MCI) Not a special CMD #define AT91C_MCI_SPCMD_INIT ((unsigned int) 0x1 << 8) // (MCI) Initialization CMD #define AT91C_MCI_SPCMD_SYNC ((unsigned int) 0x2 << 8) // (MCI) Synchronized CMD #define AT91C_MCI_SPCMD_IT_CMD ((unsigned int) 0x4 << 8) // (MCI) Interrupt command #define AT91C_MCI_SPCMD_IT_REP ((unsigned int) 0x5 << 8) // (MCI) Interrupt response #define AT91C_MCI_OPDCMD ((unsigned int) 0x1 << 11) // (MCI) Open Drain Command #define AT91C_MCI_MAXLAT ((unsigned int) 0x1 << 12) // (MCI) Maximum Latency for Command to respond #define AT91C_MCI_TRCMD ((unsigned int) 0x3 << 16) // (MCI) Transfer CMD #define AT91C_MCI_TRCMD_NO ((unsigned int) 0x0 << 16) // (MCI) No transfer #define AT91C_MCI_TRCMD_START ((unsigned int) 0x1 << 16) // (MCI) Start transfer #define AT91C_MCI_TRCMD_STOP ((unsigned int) 0x2 << 16) // (MCI) Stop transfer #define AT91C_MCI_TRDIR ((unsigned int) 0x1 << 18) // (MCI) Transfer Direction #define AT91C_MCI_TRTYP ((unsigned int) 0x3 << 19) // (MCI) Transfer Type #define AT91C_MCI_TRTYP_BLOCK ((unsigned int) 0x0 << 19) // (MCI) Block Transfer type #define AT91C_MCI_TRTYP_MULTIPLE ((unsigned int) 0x1 << 19) // (MCI) Multiple Block transfer type #define AT91C_MCI_TRTYP_STREAM ((unsigned int) 0x2 << 19) // (MCI) Stream transfer type // -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- #define AT91C_MCI_CMDRDY ((unsigned int) 0x1 << 0) // (MCI) Command Ready flag #define AT91C_MCI_RXRDY ((unsigned int) 0x1 << 1) // (MCI) RX Ready flag #define AT91C_MCI_TXRDY ((unsigned int) 0x1 << 2) // (MCI) TX Ready flag #define AT91C_MCI_BLKE ((unsigned int) 0x1 << 3) // (MCI) Data Block Transfer Ended flag #define AT91C_MCI_DTIP ((unsigned int) 0x1 << 4) // (MCI) Data Transfer in Progress flag #define AT91C_MCI_NOTBUSY ((unsigned int) 0x1 << 5) // (MCI) Data Line Not Busy flag #define AT91C_MCI_ENDRX ((unsigned int) 0x1 << 6) // (MCI) End of RX Buffer flag #define AT91C_MCI_ENDTX ((unsigned int) 0x1 << 7) // (MCI) End of TX Buffer flag #define AT91C_MCI_RXBUFF ((unsigned int) 0x1 << 14) // (MCI) RX Buffer Full flag #define AT91C_MCI_TXBUFE ((unsigned int) 0x1 << 15) // (MCI) TX Buffer Empty flag #define AT91C_MCI_RINDE ((unsigned int) 0x1 << 16) // (MCI) Response Index Error flag #define AT91C_MCI_RDIRE ((unsigned int) 0x1 << 17) // (MCI) Response Direction Error flag #define AT91C_MCI_RCRCE ((unsigned int) 0x1 << 18) // (MCI) Response CRC Error flag #define AT91C_MCI_RENDE ((unsigned int) 0x1 << 19) // (MCI) Response End Bit Error flag #define AT91C_MCI_RTOE ((unsigned int) 0x1 << 20) // (MCI) Response Time-out Error flag #define AT91C_MCI_DCRCE ((unsigned int) 0x1 << 21) // (MCI) data CRC Error flag #define AT91C_MCI_DTOE ((unsigned int) 0x1 << 22) // (MCI) Data timeout Error flag #define AT91C_MCI_OVRE ((unsigned int) 0x1 << 30) // (MCI) Overrun flag #define AT91C_MCI_UNRE ((unsigned int) 0x1 << 31) // (MCI) Underrun flag // -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- // -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- // -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Two-wire Interface // ***************************************************************************** typedef struct _AT91S_TWI { AT91_REG TWI_CR; // Control Register AT91_REG TWI_MMR; // Master Mode Register AT91_REG Reserved0[1]; // AT91_REG TWI_IADR; // Internal Address Register AT91_REG TWI_CWGR; // Clock Waveform Generator Register AT91_REG Reserved1[3]; // AT91_REG TWI_SR; // Status Register AT91_REG TWI_IER; // Interrupt Enable Register AT91_REG TWI_IDR; // Interrupt Disable Register AT91_REG TWI_IMR; // Interrupt Mask Register AT91_REG TWI_RHR; // Receive Holding Register AT91_REG TWI_THR; // Transmit Holding Register } AT91S_TWI, *AT91PS_TWI; // -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- #define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition #define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition #define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled #define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled #define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset // -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- #define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size #define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address #define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address #define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address #define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address #define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction #define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address // -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- #define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider #define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider #define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider // -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- #define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed #define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY #define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY #define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error #define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error #define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged // -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- // -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- // -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Usart // ***************************************************************************** typedef struct _AT91S_USART { AT91_REG US_CR; // Control Register AT91_REG US_MR; // Mode Register AT91_REG US_IER; // Interrupt Enable Register AT91_REG US_IDR; // Interrupt Disable Register AT91_REG US_IMR; // Interrupt Mask Register AT91_REG US_CSR; // Channel Status Register AT91_REG US_RHR; // Receiver Holding Register AT91_REG US_THR; // Transmitter Holding Register AT91_REG US_BRGR; // Baud Rate Generator Register AT91_REG US_RTOR; // Receiver Time-out Register AT91_REG US_TTGR; // Transmitter Time-guard Register AT91_REG Reserved0[5]; // AT91_REG US_FIDI; // FI_DI_Ratio Register AT91_REG US_NER; // Nb Errors Register AT91_REG Reserved1[1]; // AT91_REG US_IF; // IRDA_FILTER Register AT91_REG Reserved2[44]; // AT91_REG US_RPR; // Receive Pointer Register AT91_REG US_RCR; // Receive Counter Register AT91_REG US_TPR; // Transmit Pointer Register AT91_REG US_TCR; // Transmit Counter Register AT91_REG US_RNPR; // Receive Next Pointer Register AT91_REG US_RNCR; // Receive Next Counter Register AT91_REG US_TNPR; // Transmit Next Pointer Register AT91_REG US_TNCR; // Transmit Next Counter Register AT91_REG US_PTCR; // PDC Transfer Control Register AT91_REG US_PTSR; // PDC Transfer Status Register } AT91S_USART, *AT91PS_USART; // -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- #define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break #define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break #define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out #define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address #define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations #define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge #define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out #define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable #define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable #define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable #define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable // -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- #define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode #define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal #define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 #define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking #define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem #define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 #define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 #define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA #define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking #define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock #define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock #define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 #define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) #define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) #define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock #define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits #define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits #define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits #define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits #define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select #define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits #define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit #define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits #define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits #define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order #define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length #define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select #define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode #define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge #define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK #define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions #define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter // -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- #define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break #define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out #define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached #define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge #define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag #define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag #define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag #define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag // -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- // -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- // -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- #define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input #define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input #define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input #define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input // ***************************************************************************** // SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface // ***************************************************************************** typedef struct _AT91S_SSC { AT91_REG SSC_CR; // Control Register AT91_REG SSC_CMR; // Clock Mode Register AT91_REG Reserved0[2]; // AT91_REG SSC_RCMR; // Receive Clock ModeRegister AT91_REG SSC_RFMR; // Receive Frame Mode Register AT91_REG SSC_TCMR; // Transmit Clock Mode Register AT91_REG SSC_TFMR; // Transmit Frame Mode Register AT91_REG SSC_RHR; // Receive Holding Register AT91_REG SSC_THR; // Transmit Holding Register AT91_REG Reserved1[2]; // AT91_REG SSC_RSHR; // Receive Sync Holding Register AT91_REG SSC_TSHR; // Transmit Sync Holding Register AT91_REG Reserved2[2]; // AT91_REG SSC_SR; // Status Register AT91_REG SSC_IER; // Interrupt Enable Register AT91_REG SSC_IDR; // Interrupt Disable Register AT91_REG SSC_IMR; // Interrupt Mask Register AT91_REG Reserved3[44]; // AT91_REG SSC_RPR; // Receive Pointer Register AT91_REG SSC_RCR; // Receive Counter Register AT91_REG SSC_TPR; // Transmit Pointer Register AT91_REG SSC_TCR; // Transmit Counter Register AT91_REG SSC_RNPR; // Receive Next Pointer Register AT91_REG SSC_RNCR; // Receive Next Counter Register AT91_REG SSC_TNPR; // Transmit Next Pointer Register AT91_REG SSC_TNCR; // Transmit Next Counter Register AT91_REG SSC_PTCR; // PDC Transfer Control Register AT91_REG SSC_PTSR; // PDC Transfer Status Register } AT91S_SSC, *AT91PS_SSC; // -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- #define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable #define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable #define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable #define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable #define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset // -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- #define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection #define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock #define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal #define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin #define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection #define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only #define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output #define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output #define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion #define AT91C_SSC_CKG ((unsigned int) 0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection #define AT91C_SSC_CKG_NONE ((unsigned int) 0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock #define AT91C_SSC_CKG_LOW ((unsigned int) 0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low #define AT91C_SSC_CKG_HIGH ((unsigned int) 0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High #define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection #define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. #define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start #define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input #define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input #define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input #define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input #define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input #define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input #define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 #define AT91C_SSC_STOP ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection #define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay #define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection // -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- #define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length #define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode #define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First #define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame #define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length #define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection #define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only #define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse #define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse #define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer #define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer #define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer #define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection // -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- // -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- #define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value #define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable // -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- #define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready #define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty #define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission #define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty #define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready #define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun #define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception #define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full #define AT91C_SSC_CP0 ((unsigned int) 0x1 << 8) // (SSC) Compare 0 #define AT91C_SSC_CP1 ((unsigned int) 0x1 << 9) // (SSC) Compare 1 #define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync #define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync #define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable #define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable // -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- // -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- // -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- // ***************************************************************************** // SOFTWARE API DEFINITION FOR Serial Parallel Interface // ***************************************************************************** typedef struct _AT91S_SPI { AT91_REG SPI_CR; // Control Register AT91_REG SPI_MR; // Mode Register AT91_REG SPI_RDR; // Receive Data Register AT91_REG SPI_TDR; // Transmit Data Register AT91_REG SPI_SR; // Status Register AT91_REG SPI_IER; // Interrupt Enable Register AT91_REG SPI_IDR; // Interrupt Disable Register AT91_REG SPI_IMR; // Interrupt Mask Register AT91_REG Reserved0[4]; // AT91_REG SPI_CSR[4]; // Chip Select Register AT91_REG Reserved1[48]; // AT91_REG SPI_RPR; // Receive Pointer Register AT91_REG SPI_RCR; // Receive Counter Register AT91_REG SPI_TPR; // Transmit Pointer Register AT91_REG SPI_TCR; // Transmit Counter Register AT91_REG SPI_RNPR; // Receive Next Pointer Register AT91_REG SPI_RNCR; // Receive Next Counter Register AT91_REG SPI_TNPR; // Transmit Next Pointer Register AT91_REG SPI_TNCR; // Transmit Next Counter Register AT91_REG SPI_PTCR; // PDC Transfer Control Register AT91_REG SPI_PTSR; // PDC Transfer Status Register } AT91S_SPI, *AT91PS_SPI; // -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- #define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable #define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable #define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset #define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer // -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- #define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode #define AT91C_SPI_PS ((unsigned int) 0x1