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Cadence Design Systems Inc. R80515

The Cadence Design Systems Inc. R80515 is a Single-clock 8051-compatible IP core with 8 times more performance than legacy 80C51 (with Dhrystone v1.1 Benchmark on identical clock speed). Features: 32 I/O lines, three 16-bit Timer/Counters, 13 interrupts/4 priority levels, two serial peripheral interfaces, 16 bit multiplication-division unit, dual data pointer, compare/capture unit, 15 bit programmable watchdog timer, power management unit. Optional available: On-Chip Debug Support for Keil uVision Debugger. The R80515 IP core is compatible with FPGA and ASIC design.

*** EOL Notice ***
This device is no longer in production.

[Chip Vendor] [Distributors]

Development Tools
Compiler, Assembler, Linker, Debugger
Data Sheets
C500 Instruction Set Manual for the Cadence Design Systems Inc. R80515
C500 Instruction Set Manual
825,437 bytes
User's Manual for the Cadence Design Systems Inc. R80515
User's Manual
976,978 bytes

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Header Files
Emulators
Real-Time OS
Simulated Features

The following on-chip peripherals are simulated by the Keil Software µVision Debugger.

AGSI Drivers

The following AGSI Drivers are available for the Keil Software µVision Simulator.

AGDI Drivers

The following AGDI Drivers are available for the Keil Software µVision Debugger.


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