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Application Note 209

Using Cortex-M3 and Cortex-M4 Fault Exceptions

Cortex-M processors implement an efficient exception model that also traps illegal memory accesses and several incorrect program conditions. This application note describes the Cortex-M fault exceptions from a programmers point of view and explains the fault exceptions usage.

Revision

  • March 2016
    • Improved Fault Handlers for SHCSR from SHCSR |= 0x00007000 to
      SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk
                 |  SCB_SHCSR_BUSFAULTENA_Msk
                 |  SCB_SHCSR_MEMFAULTENA_Msk; // enable Usage-, Bus-, and MMU Fault
      
  • January 2016
    • SCB->SHP Registers: corrected parameters of NVIC_SetPriority()
    • SCB->SHCSR Register: corrected wrong SHCSR value 0x00070000 to 0x00007000
    • Implementing Fault Handlers: changed __breakpoint (0) to __BKPT (0)
    • Implementing Fault Handlers: corrected wrong SHCSR value 0x00070000 to 0x00007000
  • February 2015 - Exchanged figure 5.
  • June 2014 - Register misspellings corrected
  • November 2013 - Initial version
APNT209.PDF (668K)
Friday, March 11, 2016

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